TSV Verification via Segmented Testing and Failure Isolation
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Solution Overview
Problem
Semiconductor devices with through silicon vias (TSVs) face challenges in verifying normal operation due to failure modes like voids, incomplete filling with conductive material, and cracks, necessitating effective testing methods to ensure proper functionality.
Innovation Solution
A semiconductor device comprising multiple TSVs, an information provider for test confirmation, a detector for failure identification, and an output controller to selectively block failed TSVs, enabling sequential testing and resetting to optimize test efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all TSVs are tested sequentially to ensure complete verification, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The test process is segmented into multiple phases: initial sequential testing to identify failed TSVs, followed by parallel testing of remaining TSVs. This segmentation allows the system to achieve complete verification while reducing overall test time by transitioning from sequential to parallel processing after failure detection.
Solution Approach 2:
The testing methodology dynamically adapts based on test results. The system transitions from sequential testing mode to parallel testing mode for remaining TSVs after detecting a failure, optimizing the verification process by adjusting the testing strategy in real-time based on detected conditions.
2Reliability
If sequential testing is performed on all TSVs to identify failures, then reliability is improved, but productivity decreases
Solution Approach 1:
The TSV testing is segmented into two groups: TSVs tested sequentially to detect failures, and remaining TSVs tested in parallel. This segmentation maintains high reliability by ensuring thorough verification while improving productivity by processing multiple TSVs simultaneously in the second phase.
Solution Approach 2:
The system performs partial sequential testing (only until a failure is detected) followed by parallel testing of remaining TSVs. This partial application of sequential testing maintains reliability for detecting failed TSVs while avoiding the excessive time cost of testing all TSVs sequentially.
3Productivity
If parallel testing of multiple TSVs is performed to improve productivity, then test throughput increases, but measurement precision decreases due to difficulty in identifying specific failures
Solution Approach 1:
The testing process is segmented into sequential phase (for precise failure identification) and parallel phase (for high throughput). This segmentation allows the system to maintain measurement precision during failure detection while achieving high productivity during the testing of remaining TSVs.
Solution Approach 2:
The system performs preliminary sequential testing to identify failed TSVs before transitioning to parallel testing. This preliminary action ensures accurate failure identification is completed first, establishing a foundation for subsequent high-throughput parallel testing of remaining TSVs.
4Reliability
If complete sequential testing is performed to ensure all TSVs are verified, then reliability is improved, but loss of time increases significantly
Solution Approach 1:
The verification process is segmented into sequential testing (for complete verification of failure detection) and parallel testing (for efficient verification of remaining TSVs). This segmentation ensures complete verification reliability while significantly reducing total test duration through parallel processing of multiple TSVs simultaneously.
Solution Approach 2:
The testing system dynamically transitions from sequential to parallel mode based on test progress and detected failures. This dynamic adaptation ensures complete verification is achieved while optimizing total test duration by utilizing parallel processing capabilities for the majority of TSVs.
Data Source
AI summary
A semiconductor device may include: a plurality of output paths, which include a plurality of through silicon vias (TSVs), respectively, and suitable for transmission of test confirmation information; an information provider suitable for providing the test confirmation information to the plurality of TSVs; and an output controller suitable for selectively blocking one of the output paths including a failed one among the plurality of TSVs.