TSV Interconnect Structure With Via Buffering for 3D IC Packaging
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Solution Overview
Problem
In 3D IC packaging, direct connections between through-silicon vias (TSVs) and metal interconnects can cause high impact forces, damaging the metal interconnects, as existing design rules do not permit vias to be inserted between them, leading to design rule violations during design checks.
Innovation Solution
The introduction of extended TSV structures and models in EDA tools that allow TSVs to be connected to metal interconnects through vias, using pseudo metal layers and additional vias to buffer the impact, ensuring compatibility with current design rules and allowing 'TSV-via' connection patterns, thus reducing damage to metal interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If direct connections between TSVs and metal interconnects are used, then device complexity is reduced, but the metal interconnects suffer from high impact forces causing damage
Solution Approach 1:
The patent introduces an intermediary via structure between the TSV and the metal interconnect. This via acts as a buffer that absorbs and distributes the impact force, preventing direct transmission of high stress to the metal interconnect. The via is formed with appropriate dimensions and material properties to serve as a mechanical cushion while maintaining electrical connectivity.
Solution Approach 2:
The direct connection structure is segmented into multiple components: the TSV, the intermediary via, and the metal interconnect. This segmentation allows each component to be optimized independently for its specific function, with the via specifically designed to handle mechanical stress while the metal interconnect focuses on electrical connectivity.
2Reliability
If vias are inserted between TSVs and metal interconnects, then the susceptibility of metal interconnects to damage is reduced, but design rule violations occur with existing design rules
Solution Approach 1:
The patent modifies the design rules by changing parameters such as via dimension thresholds, spacing requirements, and material specifications. These parameter changes allow the intermediary via structure to be recognized and validated by design rule checkers, enabling the reliable connection structure to comply with manufacturing design rules.
Solution Approach 2:
The design rule set is enhanced to provide universal acceptance of the via-intermediary structure across different technology nodes and process variations. The modified rules create a multi-functional framework that simultaneously ensures mechanical reliability, electrical performance, and manufacturability.
3Object-affected harmful factors
If extended TSV structures with vias are used, then impact force buffering is achieved, but the connection pattern complexity increases
Solution Approach 1:
Instead of trying to strengthen the metal interconnect to withstand impact forces, the patent inverts the approach by making the via the stronger, more resilient component. The via is designed with superior mechanical properties to absorb impact, while the metal interconnect can be optimized for its primary electrical function without excessive thickening.
Data Source
AI summary
The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.