TSV Wafer Edge Protection for Thickness Uniformity and Crack Prevention
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Solution Overview
Problem
In the manufacturing of semiconductor devices with through silicon via (TSV) technology, thickness deviations in the edge region lead to silicon loss and cracks during processing, which affect the reliability and performance of the semiconductor device.
Innovation Solution
A method involving the formation of an edge protection layer along the remaining edge region of the semiconductor wafer after trimming, followed by exposing the through silicon via and forming upper connection pads, which prevents excessive etching and cracking by reinforcing the edge portion, thereby ensuring accurate dicing and stacking of semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the edge region of the semiconductor wafer is trimmed to remove defects, then the quality of individual chips is improved, but thickness deviation occurs leading to silicon loss and cracks
Solution Approach 1:
The edge protection layer is formed in advance before the dicing and stacking processes. This preliminary protective measure prevents thickness deviation and structural damage during subsequent processing steps, allowing the trim region to be removed safely without causing cracks or silicon loss.
Solution Approach 2:
The edge protection layer acts as a cushioning structure that compensates for the potential damage caused by removing the trim region. By providing extra thickness and mechanical support at the edge region beforehand, it prevents the harmful effects of thickness deviation and cracking during processing.
2Reliability
If the trim region is removed to improve edge quality, then chip reliability is enhanced, but excessive etching and cracking occur during processing
Solution Approach 1:
The edge protection layer serves as an intermediary protective structure between the trim region and the main chip body. It mediates the stress and mechanical forces during processing, preventing cracks from propagating into the chip while allowing the trim region to be safely removed.
3Ease of manufacture
If conventional processing is used without edge protection, then the manufacturing process is simple, but thickness deviation causes silicon loss and device failure
Solution Approach 1:
The edge protection layer is formed as a preliminary step in the manufacturing process. While this adds one process step, it prevents significant silicon loss and device failure during subsequent processing, ultimately improving overall manufacturing efficiency and yield.
Data Source
AI summary
A method for manufacturing semiconductor device includes preparing a semiconductor wafer including a first semiconductor substrate and a first through silicon via; removing a trim region of the first semiconductor substrate along an edge portion of the semiconductor wafer to form a remaining edge region; attaching the semiconductor wafer to a carrier substrate, wherein the remaining edge region is in contact with the carrier substrate; forming an edge protection layer along the remaining edge region; exposing the first through silicon via by removing a predetermined depth of the first semiconductor substrate; forming a second final passivation layer to expose the upper surface of the first through silicon via; forming a plurality of first upper connection pads on the second final passivation layer; and dicing the semiconductor wafer into a plurality of first semiconductor chips.