TSV Wafer Planarization for Accurate Wafer-on-Wafer Bonding
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Solution Overview
Problem
In the Via Middle process of semiconductor manufacturing, the uneven surface of wafers after TSV formation leads to bonding deviations during wafer on wafer bonding, affecting the electrical and thermodynamic properties of the bonded wafers and reducing the reliability of the stacked chip.
Innovation Solution
A method involving the formation of a blind hole in the wafer, deposition of a first metal material to form a TSV, removal of excess metal material, and planarization of the wafer surface, followed by the formation of a bonding pad on the planarized surface, which simplifies the manufacturing process and reduces bonding deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV is formed by depositing metal material in a blind hole, then electrical connection is achieved, but the wafer surface becomes uneven
Solution Approach 1:
The patent applies preliminary action by performing planarization processing on the wafer surface before conducting wafer-on-wafer bonding. This advance preparation removes the unevenness caused by TSV metal deposition, ensuring a flat bonding surface that prevents bonding deviations while maintaining the electrical connection functionality of the TSV structure.
2Reliability
If multiple processing steps are performed to achieve planar surface, then bonding quality is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges the planarization step into the existing TSV formation process flow. By integrating the planarization processing with the metal deposition and subsequent bonding preparation steps, the method achieves a flat bonding surface without adding significant process complexity, as the planarization is performed as part of the standard manufacturing sequence rather than as a separate additional operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method effectively improves the reliability of stacked chips by ensuring a planar surface for bonding, thereby enhancing the electrical and thermodynamic properties of the bonded wafers.
Implementation Method 1
a first metal material is deposited in the blind hole to form a TSV
Data Source
AI summary
A method for forming the semiconductor structure includes: a wafer in which a semiconductor device is formed is provided; a blind hole is formed in the wafer; a first metal material is deposited in the blind hole to form a through silicon via; and a first metal material deposited on a surface of the wafer is removed, and the surface of the wafer is planarized.