Through Substrate Via Formation for Wafer Robustness
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Solution Overview
Problem
Current semiconductor device and integrated circuit manufacturing techniques face challenges in achieving high-frequency operation and efficient heat removal while maintaining mechanical robustness, as thicker wafers required for cost-effective production complicate the formation of narrow, high-aspect-ratio through-substrate vias, leading to reduced packing density and increased manufacturing costs.
Innovation Solution
The method involves forming narrow, high-aspect-ratio front-side vias and wider, deeper back-side vias within the substrate, allowing for electrical and thermal connectivity between the front and rear surfaces without compromising wafer stability, using techniques like reactive ion etching and conductive filling, while maintaining initial wafer thickness during high-temperature processing and thinning the substrate later to minimize breakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If larger diameter wafers are used to increase manufacturing efficiency and reduce cost, then more devices can be produced simultaneously, but wafer thickness must be increased to avoid breakage which complicates TSV formation
Solution Approach 1:
The patent divides the single TSV formation process into two separate stages: front-side via formation (narrow, high-aspect-ratio) and back-side via formation (wider, deeper). This segmentation allows each via type to be optimized independently - front-side vias can be narrow to conserve device area while back-side vias can be wider to facilitate conductor filling, thereby resolving the contradiction between manufacturing efficiency and TSV formation precision
Solution Approach 2:
The patent transitions from a single-sided via formation approach to a dual-sided approach, utilizing both the front surface and back surface of the wafer for via formation. This dimensional change enables the creation of narrow front-side vias that extend partway through the wafer, then connecting them to wider back-side vias, effectively bypassing the limitation of forming narrow high-aspect-ratio vias through the entire wafer thickness
2Strength
If wafer thickness is increased to maintain mechanical robustness during manufacturing, then wafer stability is improved, but the aspect ratio of TSVs increases making etching and filling more difficult
Solution Approach 1:
The patent segments the via formation process into two distinct operations performed at different wafer thicknesses. First, narrow front-side vias are formed when the wafer is at its initial thicker state, providing mechanical robustness. Then the wafer is thinned, and wider back-side vias are formed to complete the TSVs. This segmentation allows each via formation step to occur under optimal mechanical conditions
Solution Approach 2:
The patent performs preliminary via formation on the front side before wafer thinning. The front-side vias are created when the wafer is still thick and mechanically robust, then the wafer is thinned to reduce the remaining distance for back-side via formation. This preliminary action allows narrow vias to be formed early when mechanical strength is sufficient, while the subsequent thinning eases the difficulty of completing the vias
3Ease of manufacture
If TSV area is increased to facilitate conductor filling in thicker wafers, then filling ease is improved, but device packing density decreases
Solution Approach 1:
The patent segments the via cross-section into two components: narrow front-side vias that minimize area consumption on the device surface, and wider back-side vias that facilitate conductor filling. The front-side vias occupy minimal area to preserve packing density, while the back-side vias provide sufficient width for easy conductor deposition, resolving the contradiction between filling ease and packing density
Solution Approach 2:
The patent utilizes the back surface dimension to accommodate wider via openings. By forming via openings on both the front and back surfaces of the wafer, the system can have narrow front-side vias (minimizing area impact) that connect to wider back-side vias (facilitating filling). This use of the additional dimensional space on the back surface resolves the area trade-off
4Temperature
If wafer thickness is reduced to improve heat removal efficiency, then thermal performance is improved, but wafer mechanical stability during manufacturing decreases
Solution Approach 1:
The patent performs preliminary via formation and other manufacturing steps while the wafer is at its initial thicker state, providing mechanical stability during these operations. After via formation is complete, the wafer is thinned to the final thinner state to improve heat removal efficiency. This preliminary action sequence allows the wafer to be thin in the final product for thermal performance while being thick during manufacturing for mechanical stability
Solution Approach 2:
The patent employs dynamic wafer thickness management, transitioning the wafer from a thick state during manufacturing to a thin state in the final product. The wafer thickness is adjusted at different stages of the manufacturing process - initially thick for mechanical robustness during via formation, then thinned afterward to achieve superior thermal performance in the finished device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient heat extraction and electrical coupling with minimal impact on wafer mechanical stability, maintaining robustness during manufacturing and reducing manufacturing costs by allowing for thinner finished devices and ICs with high conductivity through-substrate vias.
Implementation Method 1
using techniques like reactive ion etching
Implementation Method 2
conductive filling
Data Source
AI summary
Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20') by: (i) from the front surface (23), forming comparatively shallow vias (30, 30') of a first aspect ratio containing first conductors (36, 36') extending preferably through the first thickness (27) but not through the initial wafer (20) thickness (21), (ii) removing material (22") from the rear surface (22) to form a modified wafer (20') of smaller final thickness (21') with a new rear surface (22'), and (iii) forming from the new rear surface (22'), much deeper vias (40, 40') of second aspect ratios beneath the device region (26) with second conductors (56, 56') therein contacting the first conductors (36, 36'), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about < 40, usefully < 10 and preferably < 5.