TSV Width Variation via Etch Selectivity Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional through-silicon-via (TSV) technologies in semiconductor devices often require uniform widths, which limits their application in miniaturized and highly integrated 3D packages, where varying TSV sizes are needed for efficient electrical connections.
Innovation Solution
The semiconductor device incorporates TSVs of two or more different sizes, utilizing etch adjusting layers with distinct etch selectivities to manage the etching process, allowing for varying widths and reducing TSV bending defects during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If TSVs are formed with uniform widths according to conventional technology, then the manufacturing process is simple, but the device cannot meet the requirements of miniaturized and highly integrated 3D packages that need varying TSV sizes
Solution Approach 1:
The etching process is segmented into multiple stages with different etch adjusting layers (first etch adjusting layer and second etch adjusting layer) that have different etch selectivities. This allows independent control of etching rates at different depths, enabling formation of TSVs with different widths without requiring completely different etching processes for each TSV size.
Solution Approach 2:
Different etch adjusting layers are applied at different locations/depths within the TSV structure. The first etch adjusting layer is positioned at a first depth while the second etch adjusting layer is positioned at a second depth, creating locally differentiated etching characteristics that enable width variation in different regions of the TSV.
2Manufacturing precision
If multiple etch adjusting layers with different materials are used to achieve varying TSV widths, then precise width control is achieved, but the manufacturing process becomes more complex
Solution Approach 1:
The etch selectivity parameter is changed by using different materials for the first and second etch adjusting layers. This allows precise control of etching rates at different depths, enabling accurate TSV width control. The different materials provide different etch selectivities that can be tuned to achieve the desired width variations.
3Productivity
If TSV widths are reduced for miniaturization, then device integration is improved, but TSV bending defects increase during manufacturing
Solution Approach 1:
The etch adjusting layers are formed in advance before the final TSV etching process. These layers pre-establish the etching rate profile needed to prevent bending during subsequent etching of narrow TSVs. By preparing the etching conditions beforehand, the patent prevents bending defects in miniaturized TSVs before they occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of semiconductor devices with TSVs of diverse sizes, enhancing electrical connectivity and reducing manufacturing defects, thus improving the yield and performance of 3D semiconductor packages.
Implementation Method 1
the etch adjusting layer comprises a material having a different etch selectivity with respect to the interlayer insulating layer and the substrate
Data Source
AI summary
A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.