TSV Wire Bond Architecture for High Power ICs
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Solution Overview
Problem
In high power applications, wire bonding results in significant IR drops due to long and highly resistive bond wires, necessitating higher voltage supplies or increased costs, while flip chip techniques require larger lower chips for power and signal distribution in vertical stacks, leading to inefficiencies and increased production costs.
Innovation Solution
The use of through silicon vias (TSVs) and a backside metal layer (BML) for power and signal distribution, which reduces resistivity and allows direct connection to individual ICs, minimizing IR drops and eliminating the need for extensive routing through lower chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonding is used for connecting IC to package, then cost effectiveness and flexibility are improved, but significant IR drops occur in high power applications due to long and highly resistive bond wires
Solution Approach 1:
The patent introduces a backside metal layer (BML) on the opposite side of the substrate from the bond wires, creating a new dimensional pathway for current flow. This allows current to travel through the substrate thickness rather than along the surface, effectively adding a vertical dimension to the current path and reducing the horizontal distance bond wires must travel, thereby reducing IR drops while maintaining wire bonding benefits.
Solution Approach 2:
The BML acts as an intermediary conductive layer that receives power and signals from bond wires and redistributes them across the substrate backside. This intermediary structure reduces the reliance on long bond wires by providing a local distribution network, thereby reducing the effective length and resistance of the current path while maintaining the simplicity of wire bonding.
2Loss of energy
If flip chip technique is used with solder bumps for power and signal distribution, then IR drops are reduced, but larger lower chips are required in vertical stacks leading to increased production costs
Solution Approach 1:
The patent segments the power and signal distribution function into two parts: bond wires provide external connections while the BML provides internal distribution across the substrate backside. This segmentation allows each component to be optimized independently - bond wires for flexibility and the BML for low-resistance distribution - avoiding the need for large chips required in flip chip vertical stacks.
Solution Approach 2:
Instead of distributing power and signals through the lower chip in a vertical stack (conventional approach), the patent inverts the approach by placing the distribution network (BML) on the backside of each individual chip. This allows each chip to be self-sufficient for power distribution, eliminating the need for extensive routing through lower chips and reducing production costs.
3Adaptability or versatility
If long bond wires are used in wire bonding, then flexibility and ease of assembly are maintained, but highly resistive wires cause significant IR drops in high power applications
Solution Approach 1:
The BML creates a vertical current path through the substrate thickness, complementing the horizontal flexibility of bond wires. This dimensional change allows the system to maintain bonding flexibility while reducing the effective current path length, as current can now flow vertically through the substrate rather than relying solely on long horizontal bond wires.
Solution Approach 2:
The patent merges the advantages of wire bonding (flexibility, ease of assembly) with the advantages of short current paths (low IR drop) by combining bond wires for external connections with a BML for internal distribution. This hybrid approach retains the flexibility of wire bonding while eliminating the high resistance problem through the low-resistance BML pathway.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces IR drops, minimizes chip size, and decreases production costs by enabling direct power and signal distribution to individual ICs, improving design efficiency and reducing voltage supply noise.
Implementation Method 1
A first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV)
Implementation Method 2
A backside metal layer (BML) is formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads. The BML distributes electrical signals provided by the second subset of bonding pads
Data Source
AI summary
A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top surface, a plurality of bonding pads formed along a periphery of the bottom surface, and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads. A first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV). The BML distributes electrical signals provided by the second subset of bonding pads.