Stacked Chip Selection Using TSV Address Decoding Logic
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Solution Overview
Problem
The challenge in vertically stacked semiconductor chips is selecting and decoding individual chips due to identical terminal connections, making it difficult to activate arbitrary chips efficiently.
Innovation Solution
The use of through silicon vias (TSVs) for signal transmission between stacked chips, combined with inverter and XOR circuits in each chip, allows for decoding and selecting arbitrary chips through logical operations on address signals, simplifying the circuit configuration and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chips are vertically stacked with identical terminal connections, then chip density and integration are improved, but chip selection and decoding become difficult
Solution Approach 1:
The patent segments the address signals into multiple groups, with each group corresponding to a specific chip in the stack. By dividing the address decoding function across multiple segments (different address signal groups), each chip can be independently selected despite identical terminal connections, resolving the contradiction between high density and ease of selection.
Solution Approach 2:
The patent introduces a new dimension for chip selection by using multiple address signal groups (e.g., first, second, third address signals) that operate in different logical dimensions. This allows chips to be distinguished not by physical position or terminal variation, but by their response to different address signal dimensions, enabling selection in vertically stacked configurations.
2Ease of operation
If complex circuit changes are made to enable chip selection, then chip decoding capability is improved, but manufacturing cost and design complexity increase
Solution Approach 1:
The patent implements universal logic circuits (such as XOR gates and inverters) in each chip that can handle multiple address signal groups. These circuits serve multiple functions: they decode different address signals, enable chip selection, and maintain signal integrity. This multi-functionality reduces the need for complex, chip-specific circuitry while improving decoding capability.
Solution Approach 2:
The patent uses identical logic circuit configurations (copying the same circuit design) across all chips in the stack. Each chip contains the same XOR gates, inverters, and logic structures, which are replicated rather than customized. This copying approach simplifies manufacturing and design while enabling chip selection through address signal differentiation rather than circuit complexity.
3Ease of manufacture
If traditional wire bonding is used for stacked chips, then manufacturing process is simple, but chip size and vertical integration are limited
Solution Approach 1:
The patent replaces the mechanical wire bonding system with a direct vertical stacking approach using aligned terminal connections. Instead of using flexible wires to connect chips laterally, the invention uses vertical through-silicon vias and direct electrical contact between stacked chips, eliminating the need for wire bonding infrastructure while enabling greater vertical integration and chip size.
Data Source
AI summary
A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.