Memory Subsystem Time to Live Load Command Handling
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Solution Overview
Problem
Memory systems face inefficiencies when accessing data from lower speed memory types like NAND flash, as they often cannot meet the time-to-live requirements set by processors, leading to delayed data availability and increased processing times.
Innovation Solution
Implementing a 'time to live' parameter for load commands that allows the memory sub-system to skip operations and return an error response if data cannot be made available within the specified time, enabling data to be optionally loaded from lower speed memory to higher speed memory, such as DRAM or NVRAM, to meet the time-to-live requirement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is accessed from lower speed memory types (NAND flash), then storage capacity is improved, but data access speed deteriorates
Solution Approach 1:
The memory system is segmented into multiple memory types (NAND flash, DRAM, NVRAM) with different speed characteristics. The load command is divided into multiple operations: first checking NAND flash, then DRAM, then NVRAM in sequence, allowing the system to access data from the fastest available memory type while maintaining large storage capacity through NAND flash
Solution Approach 2:
The patent adds a time dimension to the memory access operation by introducing a time-to-live parameter. This creates a new dimension for evaluating memory access - not just whether data can be read, but whether it can be read within a specified time window. This allows the system to make intelligent decisions about which memory type to access based on both speed requirements and storage capacity considerations
2Reliability
If the memory sub-system waits for data from lower speed memory, then data completeness is improved, but processing time increases
Solution Approach 1:
The system performs preliminary actions by checking multiple memory types in a predetermined sequence (NAND flash, then DRAM, then NVRAM) before the processor needs the data. This preliminary checking ensures that if data is available in faster memory, it is identified in advance, avoiding unnecessary waiting time while still ensuring data completeness is verified
Solution Approach 2:
The memory sub-system implements skipping behavior by returning an error response immediately if data cannot be retrieved within the time-to-live window, rather than continuing to wait for slower memory operations to complete. This allows the processor to skip non-critical data processing and proceed with other tasks, reducing overall processing time while maintaining data completeness for critical operations
3Measurement precision
If the processor waits for data availability, then data accuracy is improved, but processor efficiency deteriorates
Solution Approach 1:
The system implements feedback by providing the processor with information about data availability status and estimated access times from different memory types. This feedback allows the processor to make informed decisions about whether to wait for data or proceed with alternative operations, maintaining data accuracy requirements while improving overall processor efficiency through better resource utilization
Data Source
AI summary
A memory sub-system configured to be responsive to a time to live requirement for load commands from a processor. For example, a load command issued by the processor (e.g., SoC) can include, or be associated with, an optional time to live parameter. The parameter requires that the data at the memory address be available within the time specified by the time to live parameter. When the requested data is currently in the lower speed memory (e.g., NAND flash) and not available in the higher speed memory (e.g., DRAM, NVRAM), the memory sub-system can determine that the data cannot be made available with the specified time and optionally skip the operations and return an error response immediately.