Tucked Active Region Gate Structure for Faceting Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The continued miniaturization of silicon metal oxide semiconductor field effect transistors (MOSFETs) is reaching scaling limits, making it difficult to improve performance through traditional means, necessitating new methods to enhance semiconductor device performance beyond scaling.
Innovation Solution
The method involves forming replacement gate structures over the interface between the active region and trench isolation regions, followed by the creation of embedded semiconductor regions between these structures, which are then replaced with functional gate structures, reducing faceting and parasitic capacitance by separating the embedded regions from the trench isolation regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If embedded semiconductor regions are formed directly adjacent to trench isolation regions, then device performance is improved through stress induction, but faceting occurs at the interface causing device variation
Solution Approach 1:
A dummy polysilicon region is introduced as an intermediary structure between the embedded semiconductor region and the trench isolation region. This dummy poly acts as a spacer that prevents direct contact, thereby eliminating faceting at the interface while maintaining the stress-inducing benefits of the embedded semiconductor region for device performance enhancement.
2Reliability
If embedded semiconductor regions are formed directly adjacent to trench isolation regions, then device performance is improved, but parasitic capacitance increases
Solution Approach 1:
The dummy polysilicon region serves as an intermediary that electrically isolates the embedded semiconductor region from the trench isolation region. This separation reduces the parasitic capacitance formed at the interface while preserving the beneficial stress effects on the channel, thus improving overall device performance.
3Manufacturing precision
If replacement gate structures are formed over the interface between active region and trench isolation regions, then faceting is reduced, but device complexity increases
Solution Approach 1:
Replacement gate structures are formed preliminarily over the interface regions between the active region and trench isolation regions before forming the embedded semiconductor regions. This preliminary action protects the interface areas during subsequent processing steps, preventing faceting from occurring when the embedded regions are created, while the dummy poly structure itself adds minimal complexity.
Data Source
AI summary
In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.