Tunable Multilayer Capacitor Array for High Voltage Operation
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Solution Overview
Problem
Tunable capacitors with low capacitance values at high power and voltage levels limit their application in various frequency ranges, necessitating a voltage-tunable capacitor with improved properties.
Innovation Solution
A tunable multilayer capacitor array is developed with a plurality of dielectric layers and active electrodes, utilizing a tunable dielectric material with a variable dielectric constant, allowing for capacitance tuning via a DC bias voltage, achieving initial capacitance values greater than 0.1 microFarads at operating voltages above 10 volts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional tunable capacitors are used, then capacitance can be tuned by applying voltage, but the capacitance values are relatively low at high power and voltage levels
Solution Approach 1:
The capacitor is divided into multiple discrete dielectric layers (at least 10 layers) with alternating tunable and non-tunable materials. This segmentation allows the electric field to be distributed across multiple interfaces, enhancing the overall capacitance at high voltage levels while maintaining tunability through the piezoelectric effect in specific layers.
Solution Approach 2:
The capacitor uses a composite structure combining tunable dielectric materials (exhibiting piezoelectric effect) with non-tunable dielectric materials. This composite approach enables the device to achieve both high capacitance values and voltage tunability, as the tunable layers respond to applied voltage while the non-tunable layers provide structural stability and additional capacitance.
2Volume of moving object
If the capacitor structure is made compact, then the device size is reduced, but achieving high capacitance at high voltage becomes more difficult
Solution Approach 1:
The capacitor employs a vertical stacking architecture with at least 10 dielectric layers arranged in sequence along the vertical dimension. This multi-layer configuration increases the effective capacitance volume without significantly increasing the horizontal footprint, achieving high capacitance in a compact form factor suitable for integrated circuits.
Solution Approach 2:
The capacitor structure nests multiple dielectric layers and electrode pairs within each other in a compact stacked arrangement. Each layer pair contributes to the overall capacitance, and the nested configuration allows maximum utilization of the available volume, achieving high capacitance density in a small package.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a compact, high-capacitance capacitor with low equivalent series resistance, enabling tunability across a range of high capacitance values at medium to high voltages, suitable for diverse applications including audio to RF and microwave frequencies.
Implementation Method 1
At least a portion of the dielectric layers contain a tunable dielectric material that exhibits a variable dielectric constant upon the application of an applied DC voltage across the first and second DC bias electrodes
Implementation Method 2
At least a portion of the dielectric layers contain a piezoelectric material that exhibits a variable capacitance upon application of an electric field across the first and second bias electrodes
Data Source
AI summary
A tunable multilayer capacitor array is provided. The tunable multilayer capacitor includes a plurality of tunable multilayer capacitors that are connected in parallel. The tunable multilayer capacitor has an initial capacitance value greater than about 0.1 microFarads at an operating voltage greater than about 10 volts. The tunable multilayer capacitor is configured to have a tunable capacitance by applying a DC bias voltage to the tunable multilayer capacitor array.