Tunable Capacitor With Stacked Transistor ESD Protection
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Solution Overview
Problem
Conventional ESD protection circuits in tunable capacitors face issues with diode degradation, miniaturization challenges, and insufficient reliability when handling large amplitude signals, leading to potential damage and current leakage.
Innovation Solution
A tunable capacitor design incorporating a stacked transistor ESD protection circuit with MOS transistors, where the drain and source terminals are connected in series, and gate and body terminals are connected to resistances, allowing for efficient ESD protection without turning on during normal operating conditions, even under high voltage signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a diode-based ESD protection circuit is used, then ESD protection function is provided, but the diode characteristics may change or damage due to long-time operation in breakdown region and current leakage occurs during normal operation
Solution Approach 1:
The patent employs dynamically controllable MOS transistors instead of static diodes. The transistors are controlled by control signals to switch between conducting and blocking states, allowing the protection circuit to adapt its behavior based on operating conditions. This dynamic control prevents unwanted current leakage during normal operation while maintaining ESD protection capability.
Solution Approach 2:
The patent changes the operating parameters of the protection circuit by using MOS transistors with controllable threshold voltages and channel conductances. By adjusting gate voltages and channel dimensions, the circuit can transition between different states (blocking vs. conducting), thereby controlling when ESD protection is active and when normal signal passage is permitted.
2Area of stationary object
If a single-layer ESD protection circuit is used, then area is reduced, but protection capability against high voltage ESD pulses is insufficient
Solution Approach 1:
The patent divides the ESD protection function into multiple stacked transistor layers (first ESD protection circuit with first and second MOS transistors, second ESD protection circuit with third and fourth MOS transistors). Each layer handles different aspects of ESD protection, distributing the voltage stress and improving overall protection capability while maintaining compact area through vertical stacking.
Solution Approach 2:
The patent transitions from a planar single-layer protection circuit to a three-dimensional stacked configuration. By stacking MOS transistors vertically in multiple layers with interconnected drain-source terminals, the circuit achieves enhanced ESD protection capability without proportionally increasing the chip area, effectively utilizing the vertical dimension.
3Area of stationary object
If MOS transistors are used in ESD protection circuit, then area is reduced compared to diodes, but current leakage occurs when large amplitude swing signals are applied
Solution Approach 1:
The patent implements control mechanisms that monitor the state of the protection circuit and adjust transistor gate voltages accordingly. This feedback control ensures that MOS transistors remain in the appropriate conduction or blocking state, preventing unwanted current leakage during normal operation with large amplitude signals while maintaining readiness for ESD events.
Solution Approach 2:
The patent configures the MOS transistors with predetermined threshold voltages and control signal levels that pre-establish the blocking state during normal operation. This preliminary configuration ensures that transistors automatically block current leakage before it can occur during normal signal swing, while still allowing rapid activation during ESD events.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current and prevents non-linear component generation, ensuring stable operation and extended lifespan of the tunable capacitor by maintaining a turn-off state during normal conditions and only engaging during ESD pulses.
Implementation Method 1
a switching transistor which switches on/off the connection of the first capacitor between the first terminal and the second terminal
Implementation Method 2
An electric potential difference rises due to static electricity collecting on a human body or a machine, and then the static electricity suddenly flows into a low electric potential point. This phenomenon is generally referred to as electrostatic discharge (ESD).
Data Source
Figure 1~2A
Figure 2B~3
Figure 4
AI summary
Disclosed is a tunable capacitor which includes: a variable capacitor unit placed between a first terminal and a second terminal; and an ESD protection circuit which is inserted either between the first terminal and a ground terminal or between the second terminal and the ground terminal, or is inserted both between the first terminal and a ground terminal and between the second terminal and the ground terminal.