Digitally Tunable Capacitor Biasing Without Negative Supply Voltage
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Solution Overview
Problem
Conventional methods for generating a negative supply voltage in integrated circuits are impractical or impossible in applications with stringent design constraints, such as low current and power consumption, and slow switching times, especially when charge pumps are not feasible.
Innovation Solution
A digitally tunable capacitor circuit using a series arrangement of capacitors and FET switches, where non-negative supply voltages are used to enable or disable the switches, allowing capacitance adjustment between nodes without requiring a negative supply voltage, thereby enabling fast switching and efficient RF performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods using charge pumps are used to generate negative supply voltage, then capacitance tuning is achieved, but current consumption increases and switching time slows down
Solution Approach 1:
The patent extracts and removes the charge pump component from the circuit entirely. Instead of using a charge pump to generate negative voltage, the invention uses only non-negative supply voltages (VDD and VSS) combined with FET switches and resistive networks to achieve capacitance tuning, thereby eliminating the harmful current consumption and slow switching associated with charge pumps
Solution Approach 2:
The patent changes the voltage parameter regime from requiring negative voltages to using only non-negative voltages. By using FET switches controlled by non-negative gate voltages and resistive networks to create the necessary voltage conditions, the system achieves capacitance tuning without the energy-intensive negative voltage generation
2Reliability
If conventional methods using charge pumps are used to generate negative supply voltage, then capacitance tuning is achieved, but switching time increases
Solution Approach 1:
The patent extracts and removes the charge pump component from the circuit entirely. Instead of using a charge pump to generate negative voltage, the invention uses only non-negative supply voltages (VDD and VSS) combined with FET switches and resistive networks to achieve capacitance tuning, thereby eliminating the harmful current consumption and slow switching associated with charge pumps
Solution Approach 2:
The patent replaces the charge pump mechanism (a complex voltage generation system) with a simpler FET switching mechanism controlled by non-negative voltages. The FETs act as electronic switches that can transition rapidly between on and off states, providing fast switching times compared to the slower charge pump operation
3Speed
If FET switches are used with non-negative supply voltages, then switching speed improves and power consumption decreases, but the circuit requires a specific resistive network configuration
Solution Approach 1:
The resistive network in the patent serves multiple functions simultaneously: it provides biasing for the FET switches, enables capacitance tuning by controlling switch states, and works with non-negative voltages to achieve the desired circuit behavior. This multi-functionality reduces the need for additional dedicated components
Solution Approach 2:
The resistive network acts as an intermediary between the non-negative supply voltages and the FET switches, translating the voltage inputs into appropriate gate and drain conditions for the switches. This intermediary structure enables the FETs to function correctly without requiring negative voltages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for improved RF linearity, harmonics performance, and faster switching times without the need for negative voltage generation, suitable for applications with stringent power and current consumption requirements.
Implementation Method 1
The plurality of FET switches comprises a first end FET switch and a second end FET switch... each FET switch comprises a gate resistor connecting a FET switch gate to a first supply voltage... enabling or disabling the FET switches and thereby adjusting the capacitance between the two nodes
Implementation Method 2
the resistive network comprises a plurality of resistive paths connecting a second supply voltage to drains of corresponding FET switches; the resistive network further comprises a resistive path connecting the second supply voltage to a source of the second end FET switch
Implementation Method 3
a series arrangement of two or more capacitors and a plurality of FET switches coupled between the first node and the second node... adjusting the capacitance between the two nodes
Data Source
AI summary
Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.