Tunable Command Address Protocol for Non-Volatile Memory
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Solution Overview
Problem
The interface between a storage controller and a storage medium in non-volatile memory systems acts as a bottleneck, limiting operating speed due to legacy command/address path speeds, which does not keep pace with the increasing demand for faster data transfers, especially in applications requiring access to only a few bytes of data.
Innovation Solution
The implementation of a tunable and scalable interface configuration that increases the frequency of command/address cycles by optimizing the number of IOs used for data transfer, allowing for configurations such as single, two, four, or eight IOs, and utilizing DQS as a clock signal to minimize clock delays and improve data access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If legacy interface speeds are used for command/address path, then compatibility with existing systems is maintained, but data access speed is limited and cannot keep pace with increasing storage capacity demands
Solution Approach 1:
The interface implements dynamic speed negotiation between storage controller and storage medium, allowing the command/address path to operate at different speeds based on capabilities. The storage medium can operate at faster speeds while maintaining compatibility with slower controllers through adjustable timing parameters and configurable operating modes.
Solution Approach 2:
The patent changes key timing parameters including clock signal frequency, setup and hold times, and cycle times to enable faster operation. By adjusting these parameters, the interface achieves higher data access speeds while maintaining reliable communication through optimized timing margins.
2Productivity
If the number of IOs is increased for data transfer, then data throughput is improved, but clock delays and overhead increase
Solution Approach 1:
The interface uses a subset of available IOs for command/address transfers rather than all IOs, optimizing the balance between throughput and timing overhead. This partial action approach reduces clock delays while maintaining sufficient data transfer capacity for the application requirements.
Solution Approach 2:
The data transfer process is segmented into separate phases: command/address phase using fewer IOs with optimized timing, and data phase using additional IOs for parallel transfer. This segmentation allows each phase to be optimized independently, reducing overall clock delays while maintaining high throughput.
3Loss of time
If DQS is used as clock signal to minimize delays, then command/address cycle time is reduced, but signal integrity and timing precision requirements increase
Solution Approach 1:
The interface implements feedback mechanisms including timing detection and adjustment based on actual signal behavior. The system monitors timing margins and adjusts setup/hold times dynamically to maintain signal integrity while achieving minimum cycle times, ensuring reliable operation at high speeds.
Solution Approach 2:
The system performs preliminary timing calibration and parameter optimization during initialization or low-speed operation modes. This preliminary action establishes optimal timing parameters that enable faster operation modes while maintaining signal integrity, reducing the risk of timing violations during high-speed data transfer.
Data Source
AI summary
A data storage system includes a storage medium including a plurality of memory cells; a storage controller in communication with the storage medium; and an electrical interface between the storage medium and the storage controller. The electrical interface includes an N-bit data bus; a data strobe; a command latch enable signal; and an address latch enable signal; wherein, while the command latch signal or the address latch enable signal is asserted, the storage medium is configured to: (i) receive command or address data via a subset of lines of the data bus; and (ii) latch the command or address data using the data strobe.