Tunable Delay Voltage Detection for IC Timing Attack Protection
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Solution Overview
Problem
Integrated circuits are vulnerable to voltage tampering, which can cause timing failures and compromise security functions, allowing potential data theft from secure regions.
Innovation Solution
A voltage attack detection circuit using a tunable delay circuit, error detection sequential circuit, and control circuit that operates from the same supply voltage as the logic circuitry, detecting changes in timing to generate error signals and adjust delays to indicate voltage attacks based on threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If voltage tampering is performed to lower supply voltage, then power consumption is reduced, but timing requirements are violated and security functions are compromised
Solution Approach 1:
The patent implements a voltage attack detection circuit that proactively monitors supply voltage before timing failures occur. The detection circuit includes a tunable delay circuit and error detection sequential circuit that continuously check for voltage-induced timing violations, enabling the system to take preventive action before security functions are compromised
Solution Approach 2:
The patent employs feedback mechanisms where the error detection sequential circuit generates error indications based on timing violations, which are then fed back to a control circuit. This feedback loop allows the system to detect voltage tampering attempts and respond by adjusting delay values or triggering security responses, creating a closed-loop protection mechanism
2Use of energy by moving object
If voltage tampering is performed to lower supply voltage, then power consumption is reduced, but security functions fail and data theft becomes possible
Solution Approach 1:
The patent implements preliminary anti-action by placing a voltage attack detection circuit that actively monitors for voltage tampering attempts before they can compromise security. The detection circuit is configured to identify voltage-induced timing violations and trigger security responses in advance, preventing data theft from secure regions
Solution Approach 2:
The patent introduces an intermediary detection circuit between the supply voltage and the security-critical logic circuitry. This intermediary circuit includes tunable delay elements and error detection sequential circuits that mediate the relationship between voltage variations and security functions, allowing the system to detect and respond to voltage attacks before they reach the security logic
3Measurement precision
If delay is increased in tunable delay circuit, then voltage attack detection sensitivity is improved, but timing margin is reduced
Solution Approach 1:
The patent implements dynamics by making the delay value in the delay circuit tunable and adjustable. The control circuit can dynamically adjust the delay value based on operating conditions, allowing the system to optimize between detection sensitivity and timing margin requirements. This dynamic adjustment capability enables the circuit to adapt to different voltage and timing conditions without being fixed
Data Source
AI summary
A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.