Tunable Epitaxy Structures for SRAM Read/Write Margin Balance
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Solution Overview
Problem
FinFET and GAA SRAM cells suffer from unbalanced PU and PD performance, leading to poor writing performance due to stronger PU transistor performance compared to PD transistors, resulting in a small read/write margin.
Innovation Solution
A pattern layer is used as a push-in mask to tune the width of S/D trenches, allowing for the growth of epitaxial S/D layers with varying dopant concentrations and thicknesses, which helps balance the performance of PU and PD transistors, thereby improving the read/write margin of SRAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET or GAA transistors are used in SRAM cells, then device scaling and integration are improved, but read/write margin deteriorates due to unbalanced PU and PD transistor performance
Solution Approach 1:
The patent applies local quality by creating different epitaxial S/D layer structures for PU and PD transistors. Specifically, PD transistors receive epitaxial S/D layers with higher dopant concentrations and/or greater thicknesses compared to PU transistors, thereby locally optimizing each transistor type's performance characteristics to achieve balanced SRAM cell operation
Solution Approach 2:
The patent utilizes parameter changes by varying the dopant concentration and thickness parameters of epitaxial S/D layers. By controlling these parameters differently for PU and PD transistors through selective epitaxial growth processes, the patent optimizes the performance balance between the two transistor types to improve read/write margin
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively weakens PU transistor performance and enhances the read/write margin of SRAM cells by controlling the thickness and width of epitaxial S/D features, achieving a better balance between PU and PD transistor performance.
Implementation Method 1
A pattern layer is used as a push-in mask to tune the width of S/D trenches
Implementation Method 2
allowing for the growth of epitaxial S/D layers with varying dopant concentrations and thicknesses
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.