Tunable Epitaxy Structures for SRAM PU-PD Performance Balance
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Solution Overview
Problem
FinFET and GAA SRAM cells suffer from unbalanced PU and PD performance, leading to poor writing performance due to stronger PU transistor performance compared to PD transistors, resulting in a small read/write margin.
Innovation Solution
A pattern layer is used as a push-in mask to tune the width of S/D trenches, allowing for the growth of epitaxial S/D layers with varying dopant concentrations and thicknesses, which helps balance the performance of PU and PD transistors, thereby improving the read/write margin of SRAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FinFET or GAA devices are used in SRAM fabrication, then the basic transistor functionality is achieved, but the PU transistor performance becomes too strong compared to PD transistors, resulting in small read/write margin
Solution Approach 1:
The patent applies local quality by creating different epitaxial layer structures for PU and PD transistors. Specifically, the PU transistor region receives a first epitaxial layer with specific thickness and dopant concentration, while the PD transistor region receives a second epitaxial layer with different thickness and dopant concentration. This local differentiation allows independent optimization of each transistor type's performance characteristics, balancing the previously unbalanced PU and PD transistor strengths to improve read/write margin.
Solution Approach 2:
The patent employs parameter changes by systematically varying the thickness and dopant concentration of epitaxial layers in different transistor regions. The first epitaxial layer for PU transistors has different parameters (thickness, dopant concentration) compared to the second epitaxial layer for PD transistors. By adjusting these parameters during the selective epitaxial growth process, the invention optimizes the electrical characteristics of each transistor type to achieve balanced performance and resolve the harmful effect of unbalanced transistor strengths.
2Productivity
If aggressive scaling down is performed to improve device density, then integration capacity increases, but transistor performance balance deteriorates with stronger PU performance
Solution Approach 1:
The patent maintains transistor performance balance during aggressive scaling by applying local quality through region-specific epitaxial layer structures. Even as device dimensions are reduced to increase density, the selective epitaxial growth process ensures that PU and PD transistor regions receive appropriately tailored layer thicknesses and dopant concentrations. This local differentiation compensates for the performance imbalance that typically worsens with scaling, allowing high device density to be achieved while maintaining reliable read/write margins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively weakens PU transistor performance and enhances the read/write margin of SRAM cells by controlling the thickness and width of epitaxial S/D features, achieving a better balance between PU and PD transistor performance.
Implementation Method 1
growth of epitaxial S/D layers
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.