Tunable ESD Protection Circuit for Integrated Circuits

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Solution Overview

Problem

Integrated circuit devices are increasingly susceptible to damage from electrostatic discharge (ESD) events due to shrinking gate oxide thicknesses and inadequate protection technologies, which result in breakdown voltages, poor snapback performance, and leakage issues, posing a challenge for reliable and efficient protection.

Innovation Solution

A tunable protection system comprising a tunable trigger device and a circuit protection device, where the tunable trigger device provides an adjustable activation level, and the circuit protection device offers a conductive path for ESD events while maintaining a resistive path during normal operation, allowing for optimized protection settings through adjustable junction configurations and materials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional protection circuits (grounded-gate, embedded junctions, field oxide devices) are used, then protection is provided against ESD events, but breakdown voltages are large, snapback performance is poor, and leakage increases

Engineering Contradiction:

Improveprotection against ESD eventsVSAvoidbreakdown voltage, leakage, poor snapback performance

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent employs a dynamic protection mechanism using a parasitic bipolar transistor that transitions from high-impedance state during normal operation to low-impedance state during ESD events. The trigger device dynamically controls the activation of the protection device, enabling timely response to ESD conditions while maintaining high breakdown voltage and low leakage during normal operation.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The invention changes the operational parameters of the protection circuit by using a tunable trigger device that can adjust the activation threshold. This allows optimization of the protection circuit to activate at specific voltage levels, improving snapback performance and reducing leakage while maintaining adequate breakdown voltage protection.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If gate oxide thickness is reduced for VLSI scaling, then integration density increases, but susceptibility to ESD damage increases

Engineering Contradiction:

Improveintegration densityVSAvoidsusceptibility to ESD damage

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent implements a protection circuit that activates before ESD damage can occur to the thin gate oxide. The parasitic bipolar transistor and trigger device are designed to detect impending ESD conditions and activate the protection path in advance, cushioning the vulnerable internal circuitry from direct ESD exposure while allowing continued scaling of gate oxide thickness for higher integration density.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If protection circuits are added to all I/O bonding pads, then ESD energy is dissipated safely, but device complexity and area increase

Engineering Contradiction:

ImproveESD energy dissipationVSAvoidprotection circuit area

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent designs a universal protection circuit architecture where a single parasitic bipolar transistor structure serves multiple protection functions across different I/O pads. The trigger device can be configured to protect multiple pads, and the same basic circuit topology is used throughout, reducing overall complexity while providing comprehensive ESD protection across all bonding pads.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The tunable protection system enhances reliability and performance by optimizing breakdown voltage and silicon-controlled rectifier performance, enabling timely activation of parasitic bipolar devices and achieving a more compact layout without compromising internal circuit operation.

Implementation Method 1

During an ESD event, charge is transferred between one or more pins of the integrated circuit device and another conducting object

Methodology Applied

Scientific EffectElectrostatic discharge: Electrostatic Discharge

Implementation Method 2

enabling timely activation of parasitic bipolar devices

Methodology Applied

Scientific EffectParasitic bipolar device activation:

Implementation Method 3

optimizing breakdown voltage and silicon-controlled rectifier performance

Methodology Applied

Scientific EffectBreakdown voltage:

Implementation Method 4

the circuit protection device offers a conductive path for ESD events while maintaining a resistive path during normal operation

Methodology Applied

Scientific EffectConductive path formation: Conduction (electrical)

Data Source

PatentUS9165920B2Tunable protection system for integrated circuits

Publication Date: 2015.10.20 CHARTERED SEMICON MFG LTD

AI summary

A tunable protection system including forming a tunable trigger device providing an adjustable protection activation level, forming a circuit protection device providing protection for integrated circuits, and electrically connecting the tunable trigger device and the circuit protection device to an input/output pad.