Tunable Interconnect Drivers for IC Supply Noise Reduction
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Solution Overview
Problem
Large integrated circuits face electrical noise issues due to simultaneous switching events, which increase jitter and reduce timing margins, limiting operating speeds and robustness.
Innovation Solution
The implementation of tunable interconnect drivers that selectively slow down or delay data signals to reduce power supply noise, achieved through either delaying data transmission or reducing the slew rate of interconnect drivers, particularly in shorter data paths to minimize noise impact on the power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple flip-flops switch simultaneously to achieve high operating speeds, then productivity is improved, but supply noise increases which reduces reliability
Solution Approach 1:
The patent applies periodic action by intentionally delaying data signals in a periodic or sequential manner rather than having all flip-flops switch simultaneously. This spreads the switching events over time, reducing peak supply noise while maintaining high operating speeds through controlled periodic switching patterns.
Solution Approach 2:
The patent uses preliminary action by pre-calculating and pre-establishing delay values for different data paths based on their lengths. The delay mechanism is prepared in advance with multiple delay stages, allowing the system to proactively manage switching timing to avoid supply noise peaks before they occur.
2Object-generated harmful factors
If data signals are delayed in shorter paths to reduce supply noise, then supply noise is reduced, but data transmission time increases
Solution Approach 1:
The patent applies local quality by implementing delay mechanisms only in specific locations where needed - namely in shorter data paths that would otherwise switch simultaneously with longer paths. The delay is locally applied to individual data paths based on their specific characteristics, ensuring noise reduction without unnecessarily delaying all data transmission.
Solution Approach 2:
The patent uses parameter changes by dynamically adjusting delay values based on path length characteristics. The delay mechanism can change its operation parameters (delay amount) to match the specific requirements of different data paths, optimizing the balance between noise reduction and transmission time for each individual path.
3Reliability
If timing margins are increased to ensure reliable operation, then reliability is improved, but operating speed decreases
Solution Approach 1:
By implementing periodic or sequential switching patterns through controlled delay, the patent reduces peak supply noise which in turn reduces jitter on clock and data paths. This reduction in jitter effectively increases timing margins without requiring slower operation, as the systematic spreading of switching events prevents noise-induced timing violations.
Data Source
AI summary
An IC uses a tunable interconnect driver between a data source and a data destination to selectively slow down (“de-tune”) data signals. Data sent along relatively short paths are de-tuned to reduce power supply noise during synchronous switching events. In some embodiments, the tunable interconnect driver delays data transmission relative to an un-delayed signal path, in other embodiments, the slew rate of the tunable interconnect driver is selectively reduced.