Tunable Jitter Generator Using Cascaded Delay Paths
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Solution Overview
Problem
Current jitter generators are expensive, require manual testing, and cannot generate normally distributed jitter without tradeoffs, making them unsuitable for efficient system testing.
Innovation Solution
A tunable jitter generator system using transistor-only components, implemented on FPGAs, that generates normally distributed jitter by varying delays through cascaded logical elements and combining them with a combiner, allowing for software-controlled jitter adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external jitter generators are used, then jitter generation capability is provided, but cost increases and device complexity increases
Solution Approach 1:
The patent merges the jitter generation functionality directly into the bit error rate tester by integrating a jitter generator module that uses delay elements and combiners. This integration eliminates the need for separate external jitter generators, thereby reducing overall device complexity while maintaining the capability to generate jitter for testing.
Solution Approach 2:
The patent employs delay elements that create multiple copies of the input signal with different delays. These delayed copies are then combined through combiners to generate jitter. This copying approach allows the system to generate jitter using standard logic components rather than requiring complex external jitter generation hardware.
2Reliability
If manual testing methods are used, then system testing can be performed, but productivity decreases and time consumption increases
Solution Approach 1:
The patent implements an automated testing system where the integrated jitter generator automatically generates jitter signals and the bit error rate tester automatically measures error rates without requiring manual intervention. The system self-performs the testing sequence, from jitter generation to error rate measurement, thereby significantly improving productivity and reducing time consumption compared to manual testing methods.
Solution Approach 2:
The patent incorporates a feedback mechanism where the bit error rate tester measures the error rate of the jittered signal and provides this information back to the system. This feedback enables automated analysis and evaluation of jitter tolerance, allowing the testing process to be performed automatically and efficiently without manual interpretation of results.
3Measurement precision
If normally distributed jitter is generated, then testing accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent segments the jitter generation process into multiple stages using cascade-connected delay elements. Each delay element introduces a specific delay, and the combination of multiple segmented delays creates the desired normally distributed jitter profile. This segmentation approach allows the system to achieve accurate normal distribution without requiring a single complex jitter generation mechanism.
Solution Approach 2:
The patent utilizes parameter changes in the delay elements to control the jitter distribution. By adjusting the delay parameters of the cascade-connected elements and the combining coefficients of the combiners, the system can generate normally distributed jitter. This parameter adjustment capability allows for precise control over the jitter characteristics without increasing fundamental device complexity.
Data Source
AI summary
Systems and method for generating tunable jitter are disclosed. The system can include a delay circuit having a plurality of stages and configured to receive an input signal. Each stage can include logical elements, and the delay circuit can be configured to transmit at least a first version of the input signal and a second version of the input signal through the stages such that the first version travels through a first path and the second version travels through a second path of the delay circuit. The system can include a controller that is configured to apply a number to the stages and the stages are configured to receive a portion of the number that controls which logical element of the respective stage processes the first and second versions. The system can include a combiner that combines the first version and the second version to form a jittered output signal.