Dynamically Tunable Latency in Switch Router Chips
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Solution Overview
Problem
Existing switch or router chip architectures face challenges in dynamically tuning latency based on varying requirements such as features, ports, SLAs, and pipeline stages, leading to increased complexity and repetition across different chip families, which hinders efficient low-latency performance in specific market segments.
Innovation Solution
A device or system with dynamically tunable heterogeneous latencies, utilizing hardware and software components like ASICs, FPGAs, and TCAMs to generate selector values for allocating latency modes based on qualifying parameters, allowing for configurable latency settings and bypassing pipeline stages for power saving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If existing switch or router chip architectures suppress features to meet low-latency requirements, then latency is reduced, but device complexity increases due to multiple bond-out options and repeated feature-sets across chip families
Solution Approach 1:
The patent implements dynamically tunable latency modes that can be adjusted at runtime based on traffic requirements. The system transitions from static, hard-wired latency configurations to dynamic adjustment mechanisms that allow the same chip to adapt its latency characteristics without requiring multiple specialized chip variants, thereby reducing device complexity while maintaining low-latency capabilities when needed.
Solution Approach 2:
The patent changes the latency parameter from fixed to variable by introducing configurable latency modes (e.g., low-latency mode, standard mode) that can be selected based on traffic type, port, or service-level agreements. This parameter change allows a single chip architecture to serve multiple market segments with different latency requirements without suppressing features or creating multiple chip families.
2Ease of manufacture
If existing switch or router chip architectures use hard-wired latency modes, then manufacturing is simplified, but adaptability to different networking requirements (features, ports, SLAs, stages) is reduced
Solution Approach 1:
The patent makes the switch/router chip universally adaptable to different networking requirements by implementing a single chip architecture that can dynamically configure multiple latency modes. Instead of creating specialized chip variants for different market segments, the universal chip can be programmed and configured at runtime to meet diverse requirements including different features, ports, SLAs, and pipeline stages, thereby maintaining manufacturing simplicity while maximizing adaptability.
Solution Approach 2:
The patent introduces dynamic configuration capabilities that allow latency modes to be adjusted based on runtime conditions. The system uses controllers and configuration mechanisms to change latency behavior without requiring physical reconfiguration or manufacturing changes, enabling the same chip to adapt to varying networking requirements while maintaining ease of manufacture through software/firmware control rather than hardware variants.
3Productivity
If existing switch or router chip architectures cater to high bandwidth requirements with rich networking features, then feature completeness is improved, but latency performance deteriorates for specific market segments requiring low-latency
Solution Approach 1:
The patent segments the processing pipeline into different stages that can be selectively enabled or bypassed based on traffic requirements. By dividing the network processing into discrete pipeline stages (e.g., ingress processing, switching fabric, egress processing), the system can configure certain stages to be skipped for low-latency traffic while maintaining full feature processing for other traffic types, thereby achieving both high bandwidth capability and low-latency performance for specific market segments.
Solution Approach 2:
The patent applies different quality levels of processing to different traffic flows. Instead of applying uniform feature processing to all packets, the system can apply simplified processing paths (with fewer features enabled) to traffic that requires low-latency while maintaining full feature processing for other traffic. This local quality differentiation allows the same chip to optimize latency for specific market segments without sacrificing overall feature completeness.
Data Source
AI summary
A device with dynamically tunable heterogeneous latencies includes an input port configured to receive a packet via a network, and a processing module configured to determine multiple values corresponding to a number of qualifying parameters associated with the packet. The processing module may use the values to generate a selector value and may allocate a latency mode to the packet based on the selector value.