Tunable Neural Recording Circuit for Low-Power Dense CMOS Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-density CMOS neural recording arrays face challenges in power dissipation and area constraints, making it difficult to implant them in the body while maintaining effective neural signal recording and processing.
Innovation Solution
The development of tunable sensor circuits that minimize power dissipation and silicon area, capable of compressive sensing of neural action potentials, and optimized for in-pixel processing, using analog circuits with filters and summing amplifiers to extract features from neural signals before digitization, allowing for lower bit-rate transmission and efficient data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-density CMOS arrays are used for neural recording, then the number of recording sites increases, but power dissipation and area requirements increase making implantation unsafe
Solution Approach 1:
The neural recording array is divided into multiple independent pixel circuits, each capable of autonomous signal processing. Each pixel segment contains dedicated analog filtering and feature extraction circuits that operate independently, allowing parallel processing across thousands of recording sites while maintaining low power consumption per site.
Solution Approach 2:
The patent transitions from traditional digital signal processing to analog domain processing within each pixel circuit. By performing filtering and feature extraction in the analog domain before digitization, the system reduces the data volume that requires high-power digital processing, effectively moving computation to a different dimensional space (analog vs. digital).
2Quantity of substance
If high-density CMOS arrays are used for neural recording, then the number of recording sites increases, but the silicon area required increases making implantation difficult
Solution Approach 1:
Multiple functional circuits (amplifier, filter, feature extractor, and digitizer) are merged into a single integrated pixel circuit structure. This consolidation eliminates the need for separate discrete components and interconnects, dramatically reducing the total silicon area required per recording site while maintaining high-density scalability.
Solution Approach 2:
The patent employs analog circuit implementation for signal processing functions that would traditionally require large digital logic blocks. By utilizing analog filtering and computation in the continuous domain, the system achieves equivalent processing functionality with significantly reduced area occupation compared to digital implementations.
3Loss of information
If raw spike waveforms are digitized directly, then all neural information is preserved, but the data transmission and processing burden increases
Solution Approach 1:
The patent extracts only the essential features from raw neural spike waveforms using analog filtering and feature detection circuits within each pixel. By separating and extracting only the relevant neural information (such as spike timing and amplitude characteristics) before digitization, the system preserves critical neural data while eliminating redundant information, thereby reducing transmission burden.
Solution Approach 2:
Signal processing operations (filtering, feature extraction, and compression) are performed preliminarily in the analog domain before the signal is converted to digital form. This preliminary processing reduces the data volume that subsequently requires digital transmission and storage, improving overall system productivity while maintaining information integrity.
Data Source
AI summary
A sensor circuit that is capable of sensing of neural action potentials is disclosed. The circuit can be designed to minimize power dissipation and total silicon area so that it can be incorporated into a massively parallel sensor array and ultimately implanted in the body (e.g., into the brain) in a safe manner. The circuit can also be designed to be tunable such that it can be optimized in silico prior to fabrication and can be optimized through the use of controllable current sources after fabrication.