Tunable Passive Semiconductor Elements in Stacked-Die Packages
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Solution Overview
Problem
On-chip passive semiconductor devices, such as resistors, capacitors, and inductors, suffer from lower quality factors due to higher losses and do not scale down proportionally with silicon technology nodes, leading to increased die real estate consumption and manufacturing variability, which results in performance degradation and fixed component values that cannot be adjusted post-manufacture.
Innovation Solution
The implementation of selectively configurable passive semiconductor components across multiple semiconductor dies in a stacked die package, utilizing switches to dynamically adjust resistance, capacitance, and inductance values, allowing for post-manufacture tuning and optimization of circuit performance by coupling or decoupling these components from the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If passive semiconductor devices are formed directly on the chip, then integration is improved, but quality factor deteriorates due to higher loss
Solution Approach 1:
The patent divides the passive device into multiple segments distributed across different semiconductor dies in a 3D stacked configuration. Each die contains a portion of the passive device (e.g., different sections of an inductor or capacitor), and these segments are vertically interconnected through through-silicon vias (TSVs) to form the complete device. This segmentation allows each segment to be optimized for lower loss while maintaining high integration through 3D stacking.
Solution Approach 2:
The patent transitions from planar 2D integration to 3D vertical integration by stacking multiple semiconductor dies. The passive device is extended into the vertical dimension, with components distributed across multiple layers connected via TSVs. This dimensional change enables higher integration density while reducing loss by allowing optimized current paths and reducing parasitic effects associated with planar layouts.
2Productivity
If passive devices are scaled down with silicon technology nodes, then miniaturization is improved, but die real estate consumption increases
Solution Approach 1:
The patent utilizes the vertical dimension through 3D stacking to accommodate scaled-down passive devices. By distributing device segments across multiple dies stacked vertically, the horizontal footprint on each individual die is reduced, enabling miniaturization without proportionally increasing total die real estate consumption. The vertical interconnection via TSVs provides the necessary connectivity in the third dimension.
Solution Approach 2:
The passive device is segmented across multiple dies, allowing each segment to be miniaturized and efficiently packed. This segmentation enables better utilization of die space by distributing the total device area across multiple smaller chips, thereby reducing the real estate burden on any single die while achieving overall miniaturization of the complete passive device.
3Ease of manufacture
If passive component values are fixed during fabrication, then manufacturing simplicity is improved, but performance deteriorates due to manufacturing variations
Solution Approach 1:
The patent introduces dynamic configurability to the passive device by integrating switches (such as transistor-based switches or fusion switches) that can selectively connect or disconnect different segments of the passive device. This allows the effective value (inductance, capacitance, or resistance) to be dynamically adjusted after fabrication to compensate for manufacturing variations. The switches enable reconfiguration of the device topology to achieve target performance values despite process variability.
Solution Approach 2:
The patent enables post-fabrication adjustment of passive device parameters (inductance, capacitance, resistance) by using switches to reconfigure the connectivity of device segments. By changing the effective configuration of the segmented passive device, the electrical parameters can be tuned to compensate for manufacturing variations. This parameter adjustment capability maintains reliability while preserving manufacturing simplicity, as the physical structure remains fixed but its electrical characteristics become可调.
4Adaptability or versatility
If multiple passive components are used for multi-frequency band communication, then communication versatility is improved, but device complexity increases
Solution Approach 1:
The patent employs dynamically switchable passive device segments that can be reconfigured to support multiple frequency bands. By using switches to selectively connect different segments of the passive device, a single reconfigurable passive component can replace multiple fixed passive components. This dynamic reconfiguration capability enables the same physical structure to adapt to different frequency requirements, thereby achieving communication versatility without proportionally increasing device complexity.
Solution Approach 2:
The patent designs the passive device with multi-functionality by creating a universal structure that can operate across multiple frequency bands through reconfiguration. The segmented passive device with switchable connectivity serves multiple functions (supporting different frequency bands) using a single integrated structure, rather than requiring separate dedicated components for each frequency band. This universal design reduces overall device complexity while maintaining communication versatility.
Data Source
AI summary
Passive semiconductor components and switches may be formed directly in, on, about, or across each of two or more semiconductor dies included in a stacked-die semiconductor package. At least some of the passive semiconductor components and/or switches may be formed in redistribution layers operably coupled to corresponding semiconductor dies included in the stacked-die semiconductor package. The switches may have multiple operating states and may be operably coupled to the passive semiconductor components such that one or more passive semiconductor components may be selectively included in one or more circuits or excluded from one or more circuits. The switches may be manually controlled or autonomously controlled using one or more control circuits. The one or more control circuits may receive one or more input signals containing host system information and/or data that is used to adjust or set the operating state of at least some of the switches.