Tunable Pixel Circuit Layout for Dual-Direction Scan Routing
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Solution Overview
Problem
Conventional electronic devices with tunable circuits on non-rectangular substrates face wiring and transistor layout difficulties, leading to inefficient operation due to crowded layout and differing tunable characteristics.
Innovation Solution
The electronic device incorporates a pixel circuit with scan transistors, de-multiplexer transistors, bias transistors, and storage capacitors, allowing for reduced scan lines and efficient interlaced or selective scanning of tunable circuits, enabling independent operation and fast beam-steering in bidirectional antennas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If tunable circuits are formed on a non-rectangular substrate, then the device can achieve compact layout and flexible form factor, but wiring and transistor layout become difficult and crowded
Solution Approach 1:
The substrate is divided into multiple regions with different scanning directions. First scan lines scan in a first direction for first regions, while second scan lines scan in a second direction for second regions. This segmentation allows each region to be optimized independently, resolving the layout crowding problem while maintaining manufacturability.
Solution Approach 2:
The patent introduces a dual-directional scanning approach, adding a second scanning dimension to the traditional single-direction scan. This allows circuits to be accessed from multiple directions, reducing wiring congestion and improving layout ease on non-rectangular substrates.
2Productivity
If multiple scan lines are used to drive all tunable circuits, then all circuits can be scanned efficiently, but the number of scan lines increases and layout becomes crowded
Solution Approach 1:
Different scan lines serve multiple functions by scanning different regions in different directions. First scan lines handle first regions while second scan lines handle second regions, allowing the system to maintain high scanning productivity with fewer total scan lines, thus reducing device complexity.
3Area of stationary object
If tunable circuits with different tunable characteristics are placed close together, then layout space is saved, but driving efficiency decreases due to different tuning requirements
Solution Approach 1:
The patent applies different scanning characteristics to different regions of the substrate. First regions are scanned with first scan lines in a first direction, while second regions are scanned with second scan lines in a second direction. This local optimization allows circuits with different tuning characteristics to be efficiently driven while maintaining compact layout.
Data Source
AI summary
An electronic device includes a plurality of electronic units. Each electronic unit includes a pixel circuit and a plurality of tunable circuits. The plurality of tunable circuits is coupled to the pixel circuit. and includes at least one scan transistor, a plurality of de-multiplexer transistors, a plurality of bias transistors, at least one bias-enable transistor and a plurality of storage capacitors. The plurality of de-multiplexer transistors is coupled to the at least one scan transistor. The plurality of bias transistors is coupled to the plurality of de-multiplexer transistors. The at least one bias-enable transistor is coupled to the plurality of bias transistors. The plurality of storage capacitors is coupled to a data line through the at least one scan transistor and the plurality of de-multiplexer transistors, and is coupled to at least one bias voltage line through the plurality of bias transistors and the at least one bias-enable transistor.