Tunable STT-MRAM Cache for Multi-Core Processors
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Solution Overview
Problem
Multi-core processors face increased costs and complexity due to the use of static random access memory (SRAM) in lower level caches, as well as the complexity and cost of hybrid cache systems that utilize multiple memory technologies, leading to undesirable power consumption and fabrication costs.
Innovation Solution
Implementing a multi-core processor with spin transfer torque magnetoresistive random-access memory (STT-MRAM) caches that are tailored for specific attributes such as speed, power, and density, allowing for customizable cache configurations for each processor core, reducing chip area and fabrication costs through monolithic integration of STT-MRAM cells and macros.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM is used for lower level cache, then speed and logic compatibility are improved, but chip area and power consumption increase
Solution Approach 1:
The patent changes the memory type parameter from SRAM to STT-MRAM, which fundamentally alters the trade-off characteristics. STT-MRAM provides non-volatility and lower leakage current while maintaining competitive access speeds, thereby reducing chip area and power consumption without sacrificing cache speed performance
2Speed
If SRAM is used for lower level cache, then speed is improved, but power consumption increases
Solution Approach 1:
The patent changes the memory type parameter from SRAM to STT-MRAM, which fundamentally alters the trade-off characteristics. STT-MRAM provides non-volatility and lower leakage current while maintaining competitive access speeds, thereby reducing chip area and power consumption without sacrificing cache speed performance
3Productivity
If hybrid cache with multiple memory technologies is used, then performance is improved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent applies universality by using STT-MRAM to fulfill multiple cache functions (L2, L3, or unified cache) that traditionally required different memory technologies. This single memory type can be configured through software to provide various cache hierarchies, eliminating the need for complex multi-technology hybrid caches while maintaining performance benefits
4Productivity
If inter-level or intra-level hybrid cache is used, then performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent applies universality by using STT-MRAM to fulfill multiple cache functions (L2, L3, or unified cache) that traditionally required different memory technologies. This single memory type can be configured through software to provide various cache hierarchies, eliminating the need for complex multi-technology hybrid caches while maintaining performance benefits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The customizable STT-MRAM caches improve power-performance efficiency, decrease chip area usage, and lower costs by enabling tailored memory solutions for each processor core, reducing cache miss rates and power consumption while maintaining high performance.
Implementation Method 1
spin transfer torque magnetoresistive random-access memory (STT-MRAM)
Implementation Method 2
magnetoresistive random-access memory (STT-MRAM)
Data Source
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AI summary
A multi-core processor is presented. The multi-core processor includes a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache associated with a first core of the multi-core processor and tuned according to first attributes and a second STT-MRAM cache associated with a second core of the multi-core processor and tuned according to second attributes.