Tunable Threshold Voltage Gate Stacks for FinFET CMOS
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Solution Overview
Problem
Current semiconductor fabrication methods struggle to provide separately tunable threshold voltages for n-type and p-type transistors, which is essential for optimizing power and performance in integrated circuits, as existing technologies lack efficient methods to achieve multiple work function metals in gate stacks for FinFET devices.
Innovation Solution
The method involves forming channel fins in both n-type and p-type regions of a substrate, depositing a gate dielectric, and creating work function metal stacks with shared layers to achieve distinct threshold voltages by carefully managing the thickness and composition of work function metal layers, allowing for the formation of gate stacks with tunable threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate work function metal layers are formed for n-type and p-type transistors, then separately tunable threshold voltages are achieved, but process complexity increases
Solution Approach 1:
The gate stack is segmented into multiple functional layers: a first work function metal layer (e.g., TiN) that is selectively removed from p-type regions, a second work function metal layer (e.g., Tungsten) deposited subsequently, and a gate electrode layer. This segmentation allows independent threshold voltage tuning for n-type and p-type transistors through selective material presence and removal, resolving the contradiction by enabling separate control without requiring entirely separate fabrication processes.
Solution Approach 2:
The first work function metal layer is deposited and patterned in advance before the second work function metal layer is added. This preliminary action establishes a foundation that can be selectively modified: in n-type regions, the first layer remains to provide specific work function characteristics, while in p-type regions, it is removed and replaced with the second layer. This sequential approach simplifies the overall process compared to forming completely separate metal stacks simultaneously.
2Adaptability or versatility
If multiple work function metal layers are deposited, then multiple threshold voltage levels are achieved, but manufacturing steps increase
Solution Approach 1:
Multiple work function metal layers (first work function metal layer and second work function metal layer) are merged into a single gate stack structure that is formed through a unified fabrication sequence. Rather than creating separate gates for different transistor types, the merged structure allows both n-type and p-type transistors to share the same physical gate stack, with threshold voltage differentiation achieved through selective material removal and deposition steps. This merging reduces the total number of independent manufacturing sequences required.
Solution Approach 2:
The gate stack structure serves multiple functions: it provides the gate electrode function for both n-type and p-type transistors, establishes threshold voltage characteristics through different metal layer combinations, and maintains a unified fabrication process. The first work function metal layer can serve as the primary work function metal for n-type devices while being removed for p-type devices, and the second work function metal layer provides the work function for p-type devices. This multi-functionality allows a single gate stack formation process to address multiple device requirements simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of semiconductor devices with multiple threshold voltage levels, enhancing power and performance optimization by allowing designers to select the best option for each section of the design, thereby improving the efficiency and variability of CMOS technology.
Implementation Method 1
depositing a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is deposited over the gate dielectric
Implementation Method 2
depositing a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is deposited over the gate dielectric
Data Source
AI summary
Embodiments of the invention include a wafer having gate stacks over channel fins. The wafer includes a first channel fin in an n-type region of a substrate, a second channel fin in a p-type region of the substrate, and a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is over the gate dielectric, the first channel fin in the n-type region, and the second channel fin in the p-type region. The work function metal stack over the gate dielectric and the first channel fin in the n-type region forms a first work function metal stack. The work function metal stack over the gate dielectric and the second fin in the p-type region forms a second work function metal stack. The first work function metal stack includes a shared layer of work function metal shared with the second work function metal stack.