Tunable Work Function Gate Stack for pFET Stability
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Solution Overview
Problem
The stability and control of threshold voltage (Vt) in p-type field effect transistors (pFET) devices become challenging due to the response of oxygen vacancies in high-k dielectric materials during the replacement metal gate fabrication process, especially when using untreated TiN or TaN as work function metals, leading to unstable pVt and difficulty in achieving desired performance and reliability in nFET devices.
Innovation Solution
A gate stack with a weak oxygen-scavenge stack is formed, incorporating a barrier layer such as TiN or TaN and a strong oxygen-scavenge material like TiAlC, TiAl, Al, or NbAlC, to define and adjust the p-type threshold voltage (pVt), which is more stable and reliable compared to single metal nitride layers like TiN and TaN.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If untreated TiN or TaN is used as work function metals in pFET devices, then the fabrication process is simple, but the threshold voltage becomes unstable due to oxygen vacancies in high-k dielectric materials
Solution Approach 1:
The gate stack is segmented into multiple functional layers: a first nitride layer (TiN or TaN) providing initial work function, a capping layer for protection, and a second nitride layer deposited after selective removal to provide stable work function. This segmentation allows each layer to perform its specific function independently, resolving the contradiction between fabrication simplicity and threshold voltage stability.
Solution Approach 2:
The first nitride layer is deposited in advance as a preliminary work function layer, followed by the capping layer. The selective removal and subsequent deposition of the second nitride layer is then performed. This preliminary action sequence allows the structure to be prepared in advance with a simple process, while the final stable work function is achieved through the controlled second nitride layer deposition.
2Device complexity
If a single metal nitride layer is used, then the device structure is simple, but the pVt control and reliability are poor
Solution Approach 1:
The gate stack employs a composite structure combining multiple nitride layers (TiN and/or TaN) with different functions. The first nitride layer provides initial work function, the capping layer provides protection, and the second nitride layer provides stable work function control. This composite material approach enables both structural organization and superior pVt control while managing the complexity through clear functional differentiation.
Solution Approach 2:
Different regions of the gate stack are assigned different qualities and functions: the first nitride layer region provides initial work function, the capping layer region provides protection, and the second nitride layer region provides stable work function. This local quality differentiation allows each layer to be optimized for its specific purpose, achieving reliable pVt control without unnecessary overall complexity.
3Productivity
If oxygen vacancies in high-k dielectric materials are present during replacement metal gate fabrication, then the fabrication process proceeds normally, but the pVt becomes unstable
Solution Approach 1:
The first nitride layer and second nitride layer act as intermediaries between the high-k dielectric material and the gate electrode. These nitride layers buffer and manage the oxygen vacancies in the high-k dielectric, preventing them from directly affecting the threshold voltage stability. This intermediary approach allows the fabrication process to proceed normally with high-k materials while maintaining stable pVt through the protective nitride layer structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The weak oxygen-scavenge stack effectively stabilizes pVt and improves the reliability of pFET devices, while also enhancing the performance and stability of nFET devices by reducing Vt variation and improving the overall reliability of MOSFET devices.
Implementation Method 1
depositing a scavenging layer on the first nitride layer and the capping layer
Data Source
AI summary
A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.