Tuned Semiconductor Amplifier Input Network for Harmonic Suppression
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Solution Overview
Problem
High-speed, high-power semiconductor transistors face challenges in achieving optimal performance due to limitations in second-harmonic termination and input impedance matching, which affect peak drain efficiency and output power in applications like RF communications and power amplifiers.
Innovation Solution
Incorporating a two-capacitor input network within the transistor package, where the first capacitive shunt is tuned to resonate at twice the target frequency and the second capacitive shunt is adjusted to match the input impedance, improving second-harmonic suppression and impedance matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a single capacitive shunt is used for input impedance matching, then the device complexity is reduced, but the drain efficiency and second-harmonic suppression are insufficient
Solution Approach 1:
The input matching network is segmented into two distinct capacitive shunts: a first capacitive shunt connected to the gate contact for second-harmonic suppression, and a second capacitive shunt for fundamental frequency impedance matching. This segmentation allows each capacitor to be optimized for its specific function, achieving superior drain efficiency through targeted second-harmonic termination while maintaining manageable device complexity through modular design.
2Loss of energy
If the capacitive shunt is tuned for second-harmonic suppression, then the drain efficiency improves, but the input impedance matching may be compromised
Solution Approach 1:
By separating the second-harmonic suppression function (first capacitive shunt) from the fundamental frequency impedance matching function (second capacitive shunt), the patent enables independent optimization of each function. The first capacitive shunt can be precisely tuned to resonate at twice the operating frequency for optimal second-harmonic termination, while the second capacitive shunt can be independently adjusted to achieve the desired input impedance match, eliminating the trade-off between these two performance aspects.
3Power
If no second-harmonic termination is implemented, then the device complexity is minimized, but the peak output power and efficiency are limited
Solution Approach 1:
The first capacitive shunt is configured in advance to resonate at twice the operating frequency, creating a preliminary second-harmonic termination network that suppresses second-harmonic signals before they can degrade performance. This preliminary action of suppressing harmonics enables the amplifier to achieve higher peak output power and efficiency by preventing energy loss to harmonic frequencies, while the modular capacitive structure keeps the added complexity minimal and manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances drain efficiency by up to 10% and increases peak output power, making the transistors more suitable for high-power amplifier architectures such as class-J, class-F, and Doherty amplifiers.
Implementation Method 1
altering a value of a first capacitor in a first capacitive shunt until a resonance loop of an S11 scattering-parameter curve for the transistor has a peak at a frequency that is approximately twice a target frequency for the semiconductor transistor
Implementation Method 2
altering a value of a second capacitor in a second capacitive shunt until an input impedance at an input to the second capacitive shunt is approximately equal to a target impedance value
Data Source
Figure 1A~1B
Figure 2A
Figure 2B
AI summary
Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.