Multiple Tuned Threshold Voltage CMOS Devices
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Solution Overview
Problem
Existing methods for fabricating multiple threshold voltage devices are complex and costly, particularly for non-planar semiconductor devices like FinFETs, and often result in slower operation speeds due to the need for separate masks and processing steps, which are not applicable to all device types.
Innovation Solution
A method involving multiple gate stacks with threshold voltage adjusting layers above and/or below the gate dielectric to achieve symmetric threshold voltages, allowing for the fabrication of multiple tuned threshold voltage devices on the same semiconductor wafer, applicable to both planar and non-planar devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate masks and processing steps are used to fabricate multiple threshold voltage devices, then different threshold voltages can be achieved, but fabrication complexity and costs increase
Solution Approach 1:
The patent applies local quality by introducing threshold voltage adjusting layers at specific locations (above or below the gate dielectric) only in device regions where threshold voltage modulation is needed. This allows different threshold voltages to be achieved in different device regions without requiring separate masks and processing steps for each device type, thereby reducing fabrication complexity while maintaining the ability to precisely tune threshold voltages
Solution Approach 2:
The patent implements universality by using a single set of masks and processing steps that can fabricate multiple types of devices (planar and non-planar) with different threshold voltages. The threshold voltage adjusting layers serve multiple functions: they can be positioned above or below the gate dielectric, work with different device geometries, and enable both low-power and high-performance devices to be fabricated simultaneously in the same process flow
2Manufacturing precision
If body biases are modulated to achieve multiple threshold devices, then multiple threshold voltages can be obtained, but operation speed decreases due to charging time requirements
Solution Approach 1:
The patent applies preliminary action by pre-configuring the threshold voltage characteristics during the fabrication process through the strategic placement of threshold voltage adjusting layers. This eliminates the need for dynamic body bias modulation during operation, as the threshold voltages are already tuned to the desired values during manufacturing. Consequently, devices can operate at full speed without the delays associated with charging bodies and wells required for threshold voltage modulation
3Ease of manufacture
If prior art techniques for multiple threshold voltages are applied, then planar devices can be fabricated, but non-planar devices like FinFETs cannot be manufactured
Solution Approach 1:
The patent implements universality by developing a fabrication technique that works for both planar and non-planar devices. The method of forming threshold voltage adjusting layers above or below the gate dielectric is geometry-agnostic and can be applied to planar FETs, FinFETs, trigate FETs, and other multiple gate device structures using the same process flow, thereby achieving broad adaptability across different device architectures
Data Source
AI summary
A semiconductor structure is provided that includes a first device region including a first threshold voltage adjusting layer located atop a semiconductor substrate, a gate dielectric located atop the first threshold voltage adjusting layer, and a gate conductor located atop the gate dielectric. The structure further includes a second device region including a gate dielectric located atop the semiconductor substrate, and a gate conductor located atop the gate dielectric; and a third device region including a gate dielectric located atop the semiconductor substrate, a second threshold voltage adjusting layer located atop the gate dielectric, and a gate conductor located atop the second threshold voltage adjusting layer. In the inventive structure the first threshold voltage adjusting layer includes one of an nFET threshold voltage adjusting material or a pFET threshold voltage adjusting material and the second threshold voltage adjusting layer is the other of the nFET threshold voltage adjusting material or the pFET threshold voltage adjusting material.