Tungsten Metal Lines with Air Gaps for Interconnects
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Solution Overview
Problem
Conventional semiconductor device interconnections, primarily made of Copper, face challenges in scaling below 30 nm due to high resistivity and RC delay issues, which are exacerbated by high surface and grain scattering, and reducing capacitance further compromises mechanical stability and reliability.
Innovation Solution
The use of Tungsten metal lines with air gaps between them, coupled with an interposer to manage mechanical stress, reduces resistivity and capacitance, thereby minimizing RC delay while maintaining reliability and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the pitch of Cu metal lines is reduced below 30 nm, then the device size scaling is achieved, but the resistivity increases significantly due to high surface and grain scattering
Solution Approach 1:
The patent changes the material parameter from Copper to Tungsten, which has fundamentally different electrical properties. Tungsten maintains lower resistivity at sub-30nm pitch due to its crystalline structure and electron scattering characteristics, resolving the resistivity increase problem that plagues Copper interconnects at scaled dimensions
Solution Approach 2:
The patent creates a composite structure by introducing air gaps (vacuum/air material) between Tungsten metal lines. This composite configuration reduces parasitic capacitance between adjacent interconnects, which indirectly helps maintain lower effective resistance by reducing the RC time constant, thereby addressing the resistivity issue at scaled pitch
2Reliability
If the capacitance is reduced by lowering dielectric constant, then the RC delay is reduced, but the mechanical strength of dielectric materials is weakened
Solution Approach 1:
The patent extracts the dielectric material completely from specific regions between metal lines, creating air gaps. Since air has a dielectric constant of approximately 1.0 (compared to typical low-k dielectrics of 2.0-3.0), this extraction dramatically reduces parasitic capacitance and RC delay without involving any dielectric material that could suffer from mechanical strength issues
Solution Approach 2:
The air gap structure creates a porous-like configuration in the interconnect architecture. This porous structure (with air voids between metal lines) provides excellent electrical isolation with minimal capacitance while the surrounding dielectric material maintains its mechanical integrity, as the air gaps are strategically placed rather than throughout the entire dielectric volume
3Productivity
If the pitch of metal lines is reduced, then the device density increases, but the RC delay increases due to higher resistivity
Solution Approach 1:
The material transition from Copper to Tungsten changes the fundamental resistivity parameter, allowing dense interconnect layouts to maintain lower resistance values. This enables high device density with acceptable RC delay performance
Solution Approach 2:
By extracting dielectric material to form air gaps between adjacent metal lines, the patent reduces parasitic capacitance. Since RC delay = Resistance × Capacitance, reducing capacitance through air gaps directly reduces RC delay even as device density increases and line lengths decrease
4Reliability
If Tungsten metal lines with air gaps are used, then the RC delay is reduced, but the mechanical stress from CTE mismatch increases
Solution Approach 1:
The patent introduces an interposer as an intermediary component between the Tungsten interconnect structure and the external environment. This interposer serves as a stress buffer that decouples the mechanical stress from the air gaps and Tungsten lines, allowing the electrical benefits of low RC delay to be realized without compromising structural integrity
Solution Approach 2:
The interposer structure provides beforehand cushioning against thermal expansion stress. By placing this stress-absorbing element in advance (as part of the package structure), the patent protects the sensitive air gap regions from mechanical damage that could occur during thermal cycling, thereby maintaining both low RC delay and structural reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves lower RC delay values with improved electromigration reliability and mechanical stability by utilizing Tungsten metal lines and air gaps, effectively addressing the limitations of Copper-based interconnections.
Implementation Method 1
capacitance is directly proportional to the dielectric constant (K), and current technology has reached limits on lowering K values
Implementation Method 2
the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer
Data Source
AI summary
Systems and methods are directed to a semiconductor device, which includes an integrated circuit, wherein the integrated circuit includes at least a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines, the air gaps to reduce capacitance. An interposer is coupled to the integrated circuit, to reduce stress on the two or more Tungsten lines and the at least one air gap. A laminated package substrate may be attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress.