Tungsten Buried Gate Transistor for Low Resistivity
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Solution Overview
Problem
The existing metal gate electrodes in transistors have high resistivity due to the use of metal nitrides like titanium nitride, which limits the reduction of gate resistance and can lead to de-lamination with the gate dielectric layer, affecting the transistor's performance.
Innovation Solution
A tungsten-based buried gate structure is developed, using fluorine-free tungsten layers as an interface stabilization layer and barrier layer to protect the gate dielectric and reduce resistivity, with a bulk tungsten layer filling the trench and a recessing process to form a low-resistivity buried gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal nitride (e.g., titanium nitride) is used as the barrier layer in the metal gate electrode, then the gate dielectric layer is protected from being attacked, but the resistivity increases and gate resistance cannot be reduced effectively
Solution Approach 1:
The patent changes the material parameter from metal nitride to fluorine-free tungsten, which has significantly lower resistivity while maintaining barrier functionality. This parameter change directly resolves the contradiction by providing a material that simultaneously offers protection and low resistivity.
Solution Approach 2:
The patent employs a composite structure with multiple fluorine-free tungsten layers (interface stabilization layer, barrier layer, and bulk layer) that work together to provide both protective functionality and low resistivity, overcoming the limitations of single-material approaches.
2Reliability
If metal nitride is used as the barrier layer, then interface protection is achieved, but de-lamination occurs with the gate dielectric layer
Solution Approach 1:
The patent changes the material composition from metal nitride to fluorine-free tungsten, which eliminates the de-lamination issue while maintaining interface stability. The fluorine-free composition prevents chemical reactions that cause de-lamination.
Solution Approach 2:
The patent introduces an interface stabilization layer as an intermediary between the gate dielectric and the barrier layer. This intermediate layer improves adhesion and prevents de-lamination while allowing the barrier layer to maintain its protective function.
3Reliability
If conventional metal gate electrode structure is used, then gate electrode functionality is achieved, but gate resistance remains high due to barrier layer resistivity
Solution Approach 1:
The patent changes the resistivity parameter of the gate electrode by replacing metal nitride with fluorine-free tungsten, which has inherently lower resistivity. This directly reduces gate resistance while maintaining all necessary gate electrode functions.
Solution Approach 2:
The patent creates a composite gate electrode structure with multiple fluorine-free tungsten layers that collectively provide low resistivity pathways for current flow while maintaining barrier and stabilization functions, thereby reducing overall gate resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The fluorine-free tungsten-based buried gate structure achieves lower resistivity and improved interface stability with the gate dielectric, reducing leakage current and enhancing transistor performance without the de-lamination issues associated with metal nitrides.
Implementation Method 1
forming a first fluorine-free tungsten layer as an interface stabilization layer over the gate dielectric layer, forming a second fluorine-free tungsten layer as a barrier layer over the first fluorine-free tungsten layer
Implementation Method 2
forming a bulk tungsten layer as a gate electrode over the second tungsten layer to fill the trench
Implementation Method 3
selectively recessing the third tungsten layer, the second tungsten layer and the first tungsten layer to form a buried gate structure
Data Source
AI summary
A method for fabricating a transistor that includes forming a trench in a substrate, forming a gate dielectric layer on a surface of the trench, forming a first fluorine-free tungsten layer as an interface stabilization layer over the gate dielectric layer, forming a second fluorine-free tungsten layer as a barrier layer over the first fluorine-free tungsten layer, forming a bulk tungsten layer as a gate electrode over the second tungsten layer to fill the trench, and selectively recessing the third tungsten layer, the second tungsten layer and the first tungsten layer to form a buried gate structure.


