Tungsten CMP Planarity via Shallow Dummy Patterns
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Solution Overview
Problem
The surface planarity after tungsten chemical mechanical polishing (W-CMP) is challenging due to non-uniformity in copper wiring density, leading to defects like dishing and erosion, which affects the yield and reliability of ICs, and is further compounded by the need for good surface planarity in multilayer wiring, where metal residues and defects can occur.
Innovation Solution
A fabrication method that involves forming shallower dummy patterns and contact holes using photolithography-and-etching processes, filling them with tungsten, and then removing excess tungsten through W-CMP, ensuring the dummy patterns do not contact gate electrodes or active-area silicides, thereby reducing wiring density differences and improving surface planarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If dummy patterns are formed at the same depth as contact holes through a single photolithography-and-etching process, then the process complexity is reduced, but the dummy patterns may contact gate electrodes or active-area silicides causing device performance degradation
Solution Approach 1:
The patent divides the formation of dummy patterns and contact holes into two separate photolithography-and-etching processes. This segmentation allows independent control of each structure's depth and position, ensuring dummy patterns remain shallower than contact holes and do not contact underlying device structures, thus resolving the contradiction between process simplicity and device reliability
Solution Approach 2:
The patent performs the dummy pattern formation process with controlled etch depth before forming the contact holes. This preliminary action ensures that dummy patterns are established at a safe depth level first, preventing subsequent contact hole formation from causing dummy patterns to contact gate electrodes or silicides, thereby maintaining device performance
2Adaptability or versatility
If non-uniform copper wiring density is present, then the IC design flexibility is maintained, but surface planarity deteriorates causing dishing and erosion defects
Solution Approach 1:
The patent applies local quality by forming dummy patterns specifically in blank areas where wiring density is low, rather than uniformly across the entire surface. This localized approach compensates for density variations in specific regions, improving surface planarity in those areas without affecting the overall design flexibility of the IC
Solution Approach 2:
The patent creates dummy patterns that copy the dimensional characteristics of contact holes but without penetrating through the dielectric layer. These copies provide the necessary tungsten fill to improve local density and surface planarity while maintaining the functional integrity of the actual contact holes and overall design flexibility
3Manufacturing precision
If dummy patterns are formed deeper to match contact hole depth, then the tungsten fill uniformity is improved, but the risk of contacting gate electrodes or silicides increases
Solution Approach 1:
The patent employs dynamic process control by using separate photolithography-and-etching processes with differently controlled etch depths. This allows the tungsten fill process to accommodate varying depths of contact holes and dummy patterns independently, achieving uniform tungsten fill across all structures while dynamically adjusting the etch depth to prevent dummy patterns from contacting sensitive device structures
Solution Approach 2:
The patent changes the critical parameter of etch depth between the two processes: the first process creates shallower dummy patterns, while the second process creates deeper contact holes. This parameter differentiation ensures uniform tungsten fill in both structures while maintaining a safety margin that prevents dummy patterns from contacting gate electrodes or silicides, thus resolving the contradiction between fill uniformity and device safety
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively improves surface planarity after W-CMP, preventing metal residues and defects in subsequent copper interconnection processes, ensuring reliable and high-yield production by maintaining device performance and reducing surface non-planarity deviations.
Implementation Method 1
forming contact holes and dummy patterns in the pre-metal dielectric layer by two respective processes of photolithography-and-etching
Implementation Method 2
forming contact holes and dummy patterns in the pre-metal dielectric layer by two respective processes of photolithography-and-etching
Implementation Method 3
removing the portion of the tungsten layer above the pre-metal dielectric layer with a W-CMP process
Data Source
AI summary
A fabrication method for improving surface planarity after tungsten chemical mechanical polishing (W-CMP) is disclosed. The method forms contact holes and dummy patterns by performing two respective photolithography-and-etching processes to ensure that the dummy patterns have a depth smaller than that of the contact holes. Then the method fills tungsten into the contact holes and dummy patterns and removes the redundant tungsten by a W-CMP process. With such a method, difference of wiring density between areas can be reduced by the dummy patterns, and hence a better surface planarity of the contact hole layer can be achieved. Besides, as the dummy patterns are formed in a pre-metal dielectric layer and their depth is well controlled, tungsten filled in the dummy patterns will not contact with the device area below the pre-metal dielectric layer, and thus will not affect the performance of the device.