Tungsten Gate Electrode Work Function Control for CMOS Threshold Voltage
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Solution Overview
Problem
Next-generation CMOS circuits require low voltage, low power, high performance, high density, and high reliability, but scaling of gate insulating films leads to issues like direct tunneling, impurity diffusion, and leakage current, which are not adequately addressed by existing technologies, particularly when using high-k gate insulating films with metal gate electrodes.
Innovation Solution
A semiconductor device with independently controllable threshold voltages for NMOS and PMOS is achieved by using tungsten-containing films with different work function control materials, such as carbon-containing tungsten and tungsten nitride, to form gate electrodes, which are fabricated using a method involving atomic layer deposition and post-annealing to reduce resistivity and improve interface characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of the gate insulating film is reduced to achieve high capacitance, then the capacitance increases, but leakage current increases causing problems with operating characteristics and reliability
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate insulating film from conventional silicon oxide to high-k materials, allowing increased capacitance without reducing film thickness. This resolves the contradiction by achieving high capacitance through material property change rather than geometric change.
Solution Approach 2:
The patent uses composite gate structures combining high-k gate insulating films with metal gate electrodes or polysilicon gate electrodes with specific doping profiles. This composite approach enables high capacitance while maintaining low leakage current and improved reliability.
2Ease of manufacture
If N-type polysilicon film and P-type polysilicon film are used as gate electrodes with high-k gate insulating film, then the gate electrode can be formed, but depletion is caused by impurity tunneling resulting in current decrease and unstable threshold voltage
Solution Approach 1:
The patent changes the work function parameter of the gate electrode by using metal films with specifically controlled work functions. This eliminates impurity tunneling depletion while maintaining ease of manufacture, resolving the contradiction between manufacturability and threshold voltage stability.
Solution Approach 2:
The patent introduces an intermediary layer or modifies the interface between the gate electrode and gate insulating film to prevent impurity tunneling. This intermediary mechanism eliminates depletion effects while preserving the benefits of polysilicon gate electrodes.
3Ease of manufacture
If a metal film with mid-gap work function is applied to both PMOS and NMOS, then the gate electrode can be formed, but a very high threshold voltage is required resulting in inability to satisfy low-voltage requirements
Solution Approach 1:
The patent applies different work function metal films to different transistor types (PMOS and NMOS) based on their specific electrical requirements. This local customization enables low-voltage operation for each transistor type while maintaining ease of manufacture through a systematic approach.
Solution Approach 2:
The patent segments the gate electrode material selection by transistor type, using different metal films with appropriate work functions for PMOS and NMOS devices. This segmentation enables independent optimization of threshold voltages for low-voltage operation.
4Use of energy by moving object
If a double metal gate electrode structure is used to maintain low threshold voltage, then low-voltage operation becomes possible, but the device complexity increases
Solution Approach 1:
The patent merges the gate electrode formation process with the existing CMOS fabrication process by integrating metal film deposition and patterning steps. This combining approach enables double metal gate structures for low-voltage operation while minimizing additional process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for high-speed operation with improved reliability and reduced leakage current, enabling low-voltage, high-efficiency transistor operation by independently controlling threshold voltages and enhancing the polysilicon depletion ratio and Fermi-level pinning of the gate electrodes.
Implementation Method 1
a first gate electrode formed in one of the NMOS region or the PMOS region and comprising a first tungsten-containing film containing a first work function control material; and a second gate electrode formed in the other one of the NMOS region or the PMOS region and comprising a second tungsten-containing film containing a second work function control material that is different than the first work function control material
Implementation Method 2
which are fabricated using a method involving atomic layer deposition and post-annealing to reduce resistivity and improve interface characteristics
Implementation Method 3
which are fabricated using a method involving atomic layer deposition and post-annealing to reduce resistivity and improve interface characteristics
Data Source
AI summary
The present invention provides a semiconductor device in which the threshold voltage of NMOS and the threshold voltage of PMOS are independently controllable, and a method for fabricating the same. The method includes: forming a gate insulating film over an NMOS region and a PMOS region of a semiconductor substrate; forming a carbon-containing tungsten over the gate insulating film formed over one of the NMOS region and the PMOS region; forming a carbon-containing tungsten nitride over the gate insulating film formed over the other one of the PMOS region or the NMOS region; forming a tungsten film over the carbon-containing tungsten and the carbon-containing tungsten nitride; post-annealing the carbon-containing tungsten and the carbon-containing tungsten nitride; and etching the tungsten film, the carbon-containing tungsten, and the carbon-containing tungsten nitride, to form a gate electrode in the NMOS region and the PMOS region.