Tungsten-Capped Metal Gate Stack for Lower-Resistance FinFET Contacts
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Solution Overview
Problem
The increasing demand for higher storage capacity, faster processing, and lower costs in semiconductor devices has led to the complexity of manufacturing processes, particularly in scaling down metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (FinFETs).
Innovation Solution
The fabrication process involves forming multi-gate devices with a gate structure on multiple sides of the channel region, using a gate-last process to replace a dummy gate with a high-K dielectric and metal gate stack, and employing a tungsten cap as an intermediary between the metal gate and conductive plug to reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimensions of semiconductor devices are scaled down to meet demands for higher storage capacity and faster processing, then storage capacity and processing speed are improved, but manufacturing process complexity increases
Solution Approach 1:
The gate structure is segmented into multiple distinct layers including a high-k dielectric layer and a metal gate layer, with the metal gate further divided into multiple metal layers. This segmentation allows each layer to be optimized independently for specific functions, enabling scaled-down device dimensions while maintaining manufacturability through standardized deposition processes for each layer
Solution Approach 2:
The patent implements a nested structure where a tungsten cap layer is deposited over the metal gate stack, creating a nested configuration where the metal gate is contained within the high-k dielectric, which is in turn capped by the tungsten layer. This nested arrangement allows for precise control of each layer's thickness and composition while scaling down overall device dimensions, thereby improving storage capacity and processing speed without proportionally increasing manufacturing complexity
2Reliability
If a dummy gate is replaced with a high-K dielectric and metal gate stack to improve device performance, then device performance is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The high-k dielectric layer is deposited and prepared in advance before the metal gate layers are formed. This preliminary preparation of the dielectric layer with controlled thickness and material properties enables subsequent metal gate deposition to proceed efficiently, enhancing device performance while managing manufacturing complexity through staged process implementation
Solution Approach 2:
The high-k dielectric layer serves as an intermediary between the semiconductor substrate and the metal gate layers. This intermediary layer provides electrical isolation and field control, enabling the metal gate to function effectively at scaled dimensions. The tungsten cap further acts as an intermediary protective layer that simplifies subsequent processing steps by providing a robust surface for contact formation, thereby enhancing device performance without proportionally increasing manufacturing complexity
3Reliability
If a tungsten cap is used as an intermediary between the metal gate and conductive plug to reduce resistance, then electrical conductivity is improved, but manufacturing process complexity increases
Solution Approach 1:
The tungsten cap layer serves as an intermediary between the metal gate stack and the conductive plug. This tungsten intermediary provides excellent electrical conductivity and mechanical stability, reducing resistance at the contact interface. The tungsten cap simplifies subsequent processing by providing a chemically stable surface that is easier to pattern and etch compared to directly contacting the metal gate, thereby improving electrical conductivity while actually reducing overall manufacturing complexity
Solution Approach 2:
The tungsten cap layer changes the physical and chemical parameters of the gate contact surface, providing a material with superior electrical conductivity and etch selectivity. By depositing tungsten with controlled thickness and density, the resistance parameter is reduced while the surface properties are optimized for subsequent processing steps, achieving improved electrical conductivity without proportionally increasing manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by reducing resistance and improving the manufacturing process efficiency, aligning with the demands for higher capacity and faster processing in semiconductor devices.
Implementation Method 1
employing a tungsten cap as an intermediary between the metal gate and conductive plug to reduce resistance
Data Source
AI summary
Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a low-k dielectric layer, a high-k dielectric layer, a p-type work function metal layer, an n-type work function metal layer, a silicon oxide scap layer, and a glue layer; and a continuous tungsten (W) cap over the gate structure that was formed by the gate structure being pretreated, W material being deposited and etched back, the scap layer being etched, additional W material being deposited, and unwanted W material being removed. A semiconductor fabrication method includes: receiving a gate structure; pretreating the gate structure; depositing W material on the gate structure; etching back the W material; etching the scap layer; depositing additional W material; and removing unwanted W material.