Directional Tungsten Mask Deposition for High-Aspect-Ratio Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor device fabrication, high aspect ratio features lead to erosion of dielectric spacers during etching, resulting in longer processing times and changes in feature profiles, as existing methods like PECVD cause breadloafing growth and reduce critical dimensions.
Innovation Solution
The method involves depositing a vertically grown tungsten-containing mask on field regions of a patterned etch mask, which grows vertically with minimal horizontal deposition, preserving the critical dimension and aspect ratio, and allowing simultaneous deposition and etching of the target layer using specific process conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If PECVD is used to deposit dielectric spacers, then deposition is achieved, but breadloafing growth occurs causing critical dimension reduction
Solution Approach 1:
The patent changes the deposition parameters by using plasma-enhanced chemical vapor deposition with specific gas compositions (silane and nitrogen in controlled ratios) and pressure conditions (10-100 mTorr) to achieve directional deposition that prevents breadloafing growth while maintaining critical dimensions
Solution Approach 2:
The patent introduces directionality to the deposition process by controlling plasma species transport, achieving preferential deposition in the vertical direction rather than horizontal expansion, thus preventing breadloafing growth and preserving critical dimensions
2Length of moving object
If high aspect ratio features are etched, then deep trench formation is achieved, but dielectric spacer erosion occurs
Solution Approach 1:
The patent applies a preliminary deposition of additional dielectric material on the spacer field regions before the etching process, creating a protective layer that compensates for expected erosion during deep trench etching, thereby maintaining spacer dimensions throughout the etching process
3Manufacturing precision
If multiple processing steps are used, then feature profile control is achieved, but processing time increases
Solution Approach 1:
The patent combines the deposition and etching operations into a single integrated process sequence, where dielectric material is deposited on spacer field regions and then etched in the same processing cycle, reducing the number of separate processing steps while maintaining feature profile control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains the critical dimension of the mask features, prevents erosion, and reduces processing time by integrating deposition and etching in a single step, enhancing the precision and efficiency of semiconductor substrate processing.
Implementation Method 1
depositing a vertical growth mask selectively on the field regions of the spaced apart positive features relative to the target layer... exposing the semiconductor substrate to a fluorocarbon gas and a tungsten-containing gas and igniting a plasma
Implementation Method 2
etching the target layer using both the patterned etch mask and the vertical growth mask as a mask... exposing the semiconductor substrate to a fluorocarbon gas and a tungsten-containing gas and igniting a plasma
Data Source
AI summary
Methods for forming a vertical growth mask for use in etching applications are described herein. Disclosed embodiments include introducing a tungsten-containing deposition precursor and one or more carrier gases while igniting a plasma to deposit tungsten selectively on field regions of positive features of a patterned etch mask without substantial deposition on sidewalls of the positive features or on an exposed surface of a target layer underlying the patterned etch mask.