Tungsten MOS Gate Stack for Lower Resistance and Diffusion Control
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Solution Overview
Problem
Current 22 nm technology faces challenges with Al gate material diffusion issues, high gate resistance, and limited performance enhancement for NMOS devices, which are not adequately addressed by existing solutions.
Innovation Solution
A method involving the formation of a TiAl work function layer, a 25 Å TiN barrier layer, and a 3000 Å tungsten metal layer, followed by etching to create a gate structure, which replaces the conventional Al gate material and Ti adhesive layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Al gate material is used in conventional 22 nm process, then manufacturing is simple, but gate resistance is high and diffusion problems occur
Solution Approach 1:
The patent employs a composite gate structure consisting of multiple layers: work function layer, barrier layer, and metal layer (tungsten). This composite structure combines materials with different properties to achieve low gate resistance while preventing diffusion, resolving the contradiction between reliability and complexity.
Solution Approach 2:
The patent introduces a barrier layer as an intermediary between the work function layer and the metal layer. This barrier layer mediates the interaction between materials, preventing direct contact that would cause diffusion while maintaining electrical conductivity, thus reducing gate resistance without causing diffusion problems.
2Reliability
If Al gate material is used, then manufacturing process is simple, but diffusion prevention requires additional barrier layers increasing complexity
Solution Approach 1:
The patent creates a composite gate structure where the barrier layer is integrated between the work function layer and metal layer. This composite design provides diffusion prevention as an inherent function of the structure rather than an add-on, achieving reliability without excessive complexity.
Solution Approach 2:
The patent merges the functions of diffusion prevention and electrical conductivity into a single integrated gate structure. The barrier layer simultaneously serves as a diffusion barrier and an conductive pathway, combining multiple functions into one structure to reduce overall complexity.
Data Source
AI summary
The present disclosure provides a method for improving performance of a MOS device, including: providing a work function layer; forming a barrier layer on the work function layer; forming a metal layer on the barrier layer, wherein the material of the metal layer is tungsten, and the thickness of the metal layer is 3000 Å; and etching the metal layer, the barrier layer, and the work function layer to form a gate structure. The present disclosure replaces an Al gate material in the conventional 22 nm process with tungsten, and replaces a Ti adhesive layer and a TiN barrier layer below an Al gate with a TiN barrier layer of 25 Å. The present disclosure greatly reduces a gate resistance of the MOS device and enhances a tensile stress of a channel, thereby improving the performance of the NMOS device.