Tungsten Nitride Blocking Layer for Boron Diffusion Control

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Solution Overview

Problem

In semiconductor manufacturing, the diffusion of boron (B) into the metal gate and gate dielectric layer during the Atomic Layer Deposition (ALD) process of tungsten (W) affects the performance and reliability of devices, especially in advanced CMOSFETs where high-quality metal layers with good step coverage are required for sizes less than 40 nm.

Innovation Solution

A method involving the formation of a tungsten nitride (WN) blocking layer by injecting nitrogen ions and performing annealing, followed by preheating and forming a Si diffusion blocking layer, and using alternating reactions with Si-containing and borane gases to control the deposition of W, prevents boron diffusion and enhances adhesion and planarization of the W layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If W is prepared through ALD using B2H6 as precursor, then high-quality metal layer with good step coverage is achieved, but B diffuses into metal gate and gate dielectric layer affecting device performance

Engineering Contradiction:
Improvestep coverageVSAvoiddevice performance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A BN blocking layer is introduced as an intermediary between the W layer and the gate structure. This blocking layer acts as a mediator that prevents B diffusion into the gate and dielectric while allowing the W layer to maintain its high-quality deposition characteristics through ALD process

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The W layer formation process is segmented into multiple stages: first forming a initial W layer, then forming the BN blocking layer, and finally forming the main W filling layer. This segmentation allows the blocking layer to be inserted to prevent B diffusion while maintaining the benefits of ALD deposition

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If conventional CVD or PVD is used to form metal filling layer, then process is simpler, but step coverage is poor and ultrathin metal layer control is difficult

Engineering Contradiction:
Improveprocess simplicityVSAvoidstep coverage
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The deposition method is changed from conventional CVD/PVD to ALD process. This parameter change enables precise control of ultrathin metal layers and achieves excellent step coverage and gap filling capability, meeting the requirements for devices with size less than 40 nm

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively blocks boron ions from penetrating into the metal gate and gate dielectric layers, improving the reliability and reducing gate resistance while maintaining high-quality metal layer deposition, meeting the requirements for advanced semiconductor devices.

Implementation Method 1

An Atomic Layer Deposition (ALD) process is surface reaction-limited based on chemical absorption

Methodology Applied
Scientific EffectChemical absorption: Chemisorption

Implementation Method 2

forming the WN blocking layer by injecting the N ions and performing annealing

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 3

forming a Si diffusion blocking layer by decomposing Si-containing gas

Methodology Applied
Scientific EffectDecomposition: Decomposition (biological)

Implementation Method 4

filling with W through an Atomic Layer Deposition (ALD) process

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS10115804B2Method for manufacturing semiconductor device
Publication Date: 2018.10.30 INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
  • US10115804B2 patent drawing
  • US10115804B2 patent drawing
  • US10115804B2 patent drawing

AI summary

A method for manufacturing a semiconductor device, comprising: forming a gate trench on a substrate; forming a gate dielectric layer and a metal gate layer thereon in the gate trench; forming a first tungsten (W) layer on a surface of the metal gate layer, and forming a tungsten nitride (WN) blocking layer by injecting nitrogen (N) ions; and filling with W through an atomic layer deposition (ALD) process. The blocking layer prevents ions in the precursors from aggregating on an interface and penetrating into the metal gate layer and the gate dielectric layer. At the same time, adhesion of W is enhanced, a process window of W during planarization is increased, reliability of the device is improved and the gate resistance is further reduced.