Tungsten Seed Layer Grain Control for Low Resistivity
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Solution Overview
Problem
As the critical dimensions of conductive structures in semiconductor devices decrease, conventional materials exhibit increased resistance, making it challenging to maintain suitable electrical properties, often requiring exotic materials or complex device designs to mitigate this issue.
Innovation Solution
The use of a seed layer comprising tungsten and another material, such as silicon, to inhibit nucleation and promote the formation of tungsten fill material with larger grain sizes, resulting in improved conductivity, with a majority of the tungsten being in the alpha phase and exhibiting grain sizes of 20 nm or greater.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional conductive structures are formed with reduced critical dimensions, then device density and integration are improved, but resistance increases making it difficult to maintain suitable electrical properties
Solution Approach 1:
The patent changes the physical and chemical parameters of tungsten by controlling grain size (increasing to 20nm or greater) and crystal phase (achieving at least 50% alpha phase) through seed layer formation and controlled deposition processes. These parameter changes reduce resistivity and maintain electrical properties even at reduced critical dimensions
Solution Approach 2:
The patent uses a composite structure consisting of a seed layer (comprising tungsten and another material such as silicon) combined with tungsten fill material. This composite approach enables control over nucleation and grain growth, achieving large-grained alpha-phase tungsten with superior electrical properties
2Reliability
If conventional conductive structures use larger line widths to maintain suitable electrical properties, then resistance is reduced, but device density and integration are compromised
Solution Approach 1:
The patent fundamentally changes the resistivity parameter of tungsten conductive structures by controlling microstructure (grain size and crystal phase). By achieving large grains (≥20nm) and alpha-phase dominance through seed layer techniques, the resistivity is reduced enough to allow smaller line widths while maintaining electrical properties, thereby enabling higher device density
3Reliability
If exotic materials or complex processing methods are used to form suitable conductive structures, then electrical properties are improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming a seed layer before depositing the bulk tungsten fill material. This seed layer pre-establishes the conditions for large-grained alpha-phase tungsten formation, simplifying the overall process compared to using exotic materials while achieving the desired electrical properties
Solution Approach 2:
Instead of using exotic materials, the patent achieves improved electrical properties by changing the processing parameters of conventional tungsten deposition - specifically controlling temperature, pressure, and deposition rate to promote alpha-phase formation and large grain growth, thereby maintaining manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the resistance of tungsten conductive structures, enabling smaller dimensions while maintaining acceptable electrical properties, with resistivity values as low as 2-4 Ω/sq for structures with dimensions of 20 nm wide and 65-100 nm deep.
Implementation Method 1
forming a seed layer comprising tungsten and silicon in the recess; and forming a tungsten fill over the seed layer
Implementation Method 2
a majority of the tungsten of the tungsten fill has grains having a longest dimension of at least 20 nm
Implementation Method 3
a majority of the tungsten is in the alpha phase
Data Source
AI summary
Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.