Tungsten Silicide Gate Contact Stack for Resistance Uniformity
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability due to issues with resistance uniformity, particularly in the fabrication of conductive layer stacks and gate contacts.
Innovation Solution
A conductive layer stack is fabricated with an intervening layer of tungsten silicide and a filler layer of tungsten, both positioned on a titanium nitride under-layer with a columnar grain structure, where the intervening layer's thickness is greater than 4.1 nm, and the filler layer is deposited using germanium-containing reducing agents to promote alpha-tungsten growth, reducing defects and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the intervening layer thickness is reduced to scale down the semiconductor device, then the device dimensions are reduced, but resistance uniformity deteriorates
Solution Approach 1:
The patent changes the material composition parameters of the intervening layer by incorporating silicon into the tungsten layer, forming a tungsten-silicon alloy. This compositional parameter change allows the layer to maintain lower resistance and better uniformity even at reduced thicknesses, enabling device scaling while preserving electrical performance
Solution Approach 2:
The patent creates a composite material structure by forming an alloy of tungsten and silicon in the intervening layer. This composite approach combines the low resistance properties of tungsten with the beneficial electrical characteristics introduced by silicon, achieving improved resistance uniformity that enables thinner layer designs for scaled-down devices
2Reliability
If the filler layer is deposited with thinner nucleation layer to reduce defects, then the defect density is reduced, but alpha-tungsten growth is inhibited
Solution Approach 1:
The patent modifies the deposition parameters by introducing germanium-containing reducing agents during the filler layer deposition process. This parameter change enables the formation of alpha-tungsten crystal structure even with thinner nucleation layers, maintaining material stability while reducing defects associated with thicker nucleation layers
3Reliability
If the intervening layer thickness is increased to improve resistance uniformity, then resistance uniformity is improved, but the device complexity increases
Solution Approach 1:
The patent changes the material composition parameter by forming a tungsten-silicon alloy in the intervening layer, which improves resistance uniformity through enhanced electrical properties. This compositional modification achieves the reliability improvement without requiring additional layers or complex structural modifications, thereby avoiding increased device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability, yield, and performance of semiconductor devices by improving resistance uniformity and reducing defects in the filler layer, leading to improved device performance.
Implementation Method 1
the filler layer deposited using germanium-containing reducing agents may reduce resistance, thin filler nucleation layer that yield alpha-tungsten growth
Data Source
AI summary
The present application discloses a method for fabricating a conductive layer stack. The method includes forming an intervening layer on an under-layer; and forming a filler layer on the intervening layer, wherein the filler layer comprises tungsten. The intervening layer comprises tungsten silicide and a thickness of the intervening layer is greater than 4.1 nm. The under-layer comprises titanium nitride and comprises a columnar grain structure.