Tungsten Via Protrusion Formation to Prevent CMP Recess
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Solution Overview
Problem
The use of metal tungsten (W) in vias leads to metal corrosion during chemical mechanical polishing (CMP), resulting in tungsten recesses that hinder full connection with back-end-of-line interconnection metals, causing high resistance or open circuits, and existing methods fail to address issues of selectivity ratio, uneven polishing, and scratches, reducing chip yield.
Innovation Solution
A two-step process involving first-time metal CMP followed by second-time dielectric etch back, specifically using Certas etching, to form a metal protrusion that ensures full contact with upper metal interconnection layers, avoiding recesses and scratches, with improved selectivity and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If W CMP is performed to remove excess W, then the via structure is planarized, but metal corrosion occurs causing tungsten recess
Solution Approach 1:
The polishing process is divided into two separate steps: first polishing to remove excess W and achieve planarization, and second overpolishing with a different slurry to form a W protrusion. This segmentation allows each step to optimize for its specific function without the trade-off present in single-step polishing.
Solution Approach 2:
The invention changes the parameters of the polishing slurry between two steps: the first polishing uses a standard slurry, while the second overpolishing uses a slurry with higher selectivity ratio for oxide. This parameter change enables the formation of W protrusion to compensate for corrosion-induced recess.
2Reliability
If existing improvement method uses two polishing steps with higher selectivity ratio slurry, then W protrusion is formed to compensate for W recess, but poor selectivity ratio and uneven polishing rate remain
Solution Approach 1:
The invention replaces the mechanical polishing system with a chemical etching system for the second step. Instead of using mechanical CMP to form the protrusion, chemical etching is used to selectively remove dielectric material, allowing the W protrusion to emerge naturally. This substitution eliminates mechanical scratches and achieves better uniformity.
Solution Approach 2:
The invention introduces a dielectric oxide layer as an intermediary material that enables the formation of W protrusion. By overetching this dielectric layer through chemical etching, the W protrusion is revealed without direct mechanical contact, avoiding scratches while maintaining reliability.
3Manufacturing precision
If W CMP is performed to planarize the via, then excess W is removed, but scratches are formed on V0 W affecting device performance
Solution Approach 1:
The invention replaces mechanical polishing with chemical etching for the second processing step. By using chemical etching to remove dielectric material and reveal the W protrusion, mechanical contact is eliminated, thereby preventing scratches on the V0 W surface while still achieving the desired via structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances via structure uniformity and contact reliability, reducing high resistance and open circuits, thereby improving device performance and yield, particularly in small process nodes.
Implementation Method 1
a polishing slurry may electrochemically react with W to cause metal corrosion
Implementation Method 2
second-time dielectric etch back, where the second-time dielectric etch back selectively etches the first dielectric layer
Data Source
AI summary
The present disclosure discloses a method for manufacturing a via, including: forming a first dielectric layer on the surface of an underlying structure; performing patterned etching on the first dielectric layer to form a via opening; forming a first metal layer; performing first-time metal CMP to remove the first metal layer on the outer surface of the via opening, where a top surface of the first metal layer in the via opening is located below a top surface of the first dielectric layer; performing second-time dielectric etch back, to selectively etch the first dielectric layer, lower the top surface of the first dielectric layer as being below the top surface of the first metal layer, and form a metal protrusion of a via; and forming a pattern of an upper metal interconnection layer.