Selective Tungsten Via Fill for Interconnect Resistance
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in reliably forming interconnects with sub-100 nm features, particularly in reducing via resistance to enhance chip performance and density, as conventional methods result in high interconnect resistance due to materials used in the barrier and liner layers, which affects RC delay and power management.
Innovation Solution
A selective metal via fill method is employed, involving pre-treatment processes to prepare the interconnects for a bottom-up growth of a metal material like tungsten, reducing via resistance while maintaining reliability and line resistance requirements, and bifurcating the metal fill process by using different materials for the via and trench to decrease overall resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional barrier and liner layer materials are used in via fill, then manufacturing process is simplified, but via resistance increases
Solution Approach 1:
The patent divides the via fill process into two distinct stages: a first fill process using conventional barrier/liner materials for trench regions, and a second fill process using tungsten for via regions. This segmentation allows each material to be optimized for its specific function - the barrier/liner materials provide good adhesion and coverage for trenches, while tungsten provides low resistance for vias, thereby resolving the contradiction between simplified processing and low via resistance.
Solution Approach 2:
The patent applies different materials to different locations within the interconnect structure - using barrier/liner materials specifically for trench regions and tungsten specifically for via regions. This local differentiation ensures that each region receives the material best suited for its electrical and structural requirements, achieving low via resistance without compromising the overall manufacturing process.
2Reliability
If dual metal fill process is implemented, then via resistance decreases, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by first filling trenches with barrier/liner materials before proceeding to via fill with tungsten. The first fill process prepares the structure by establishing proper material layers in trench regions, and may include preliminary treatments of via regions to ensure optimal conditions for subsequent tungsten deposition. This preliminary action sequence makes the complex dual-fill process more manageable and manufacturable.
Solution Approach 2:
The patent implements the dual metal fill process as two periodic, sequential operations rather than a single continuous process. The first fill operation completes trench regions, then the second fill operation addresses via regions. This periodic approach allows each fill operation to be independently optimized and controlled, reducing the practical manufacturing complexity despite the increased process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively lowers via resistance and meets reliability and line resistance requirements, improving chip performance by reducing RC delay and power consumption, while ensuring integration and reliability aspects are met.
Implementation Method 1
A bottom of the via is pre-treated using a first pre-treatment procedure
Implementation Method 2
A sidewall of the via is pre-treated using a second pre-treatment procedure
Implementation Method 3
A first metal fill material of a first type is deposited on the stack, in the via
Implementation Method 4
A second metal fill material of a second type is deposited on the stack, in the trench
Data Source
AI summary
Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.