Tuning Fork Via Structures for Low Resistance and High Routing Porosity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuit manufacturing, the use of wide wires for reducing via resistance leads to porosity problems due to blockage of potential via locations, resulting in inefficiencies and increased signal propagation delays, particularly at advanced process nodes like 45 nm and smaller, where via resistance and wire resistance become limiting factors.
Innovation Solution
The implementation of a 'Tuning Fork Via' structure, which includes a first and second forked conductive layer with conductive vias connecting them, allowing for efficient porosity and reduced resistance by splitting wide wires into forked structures that maintain continuity and minimize blockage, enabling flexible routing and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wide wires are used to reduce via resistance, then via resistance decreases, but routing porosity deteriorates due to blockage of potential via locations
Solution Approach 1:
The patent segments wide wires into forked structures with multiple narrower conductive paths. Instead of using a single wide wire that blocks routing, the wire is divided into multiple segments that can be routed around obstacles, maintaining electrical connectivity while improving routing flexibility and porosity.
Solution Approach 2:
The patent introduces vertical stacking of metal layers to resolve routing conflicts. When horizontal routing is blocked by wide wires, the design can transition to adjacent metal layers, using the vertical dimension to maintain routing porosity and avoid blockage while preserving electrical connectivity through via structures.
2Reliability
If redundant vias are implemented to reduce resistance, then via resistance decreases, but manufacturing complexity increases due to gridded via constraints
Solution Approach 1:
The patent designs forked conductor structures that serve multiple functions simultaneously: they provide redundant electrical paths for low resistance, create natural via locations at fork junctions, and maintain routing flexibility. This multi-functionality reduces the need for separate redundant via structures while achieving the same resistance reduction goal.
Solution Approach 2:
The patent pre-establishes forked conductor patterns during the design phase that anticipate future via placement needs. The forked structures are designed with inherent via locations at their junctions, so when routing is performed, via placements naturally occur at these pre-prepared locations, simplifying the overall via structure and reducing manufacturing complexity.
Data Source
AI summary
An integrated circuit structure includes a first conductive layer (MET4) including a first forked conductive structure (310), an insulating layer (320, ILD45) substantially disposed over the first forked conductive structure (310), a plurality of conductive vias (331-334) through the insulating layer (ILD45) and electrically connecting with the first forked conductive structure (310), and a second conductive layer (MET5) including a second forked conductive structure (340) substantially disposed over at least a portion of the insulating layer (ILD45) and generally perpendicular to the first forked conductive structure (310), the plurality of conductive vias (331-334) electrically connecting with the second forked conductive structure (340). Other structures, devices, and processes are also disclosed.