Tunnel Diode Memory Fabrication via Stencil Process
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Previous tunnel diode memory designs face challenges in manufacturing defect-free large memories due to difficulties in electrically matching pairs of tunnel diodes, and existing capacitive coupling methods are not efficiently integrated with high-frequency, high-density SRAM memory arrays.
Innovation Solution
The design incorporates tunnel diodes serially connected between voltage lines and coupled to data lines through capacitors, arranged in a two-dimensional array with perpendicular ground and clock lines, using a stencil fabrication process that eliminates masking variations and allows for the construction of memory cores and control logic without masks, enabling efficient and economical manufacturing of high-speed memory cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pairs of tunnel diodes are used in memory design, then high speed and compact size are achieved, but electrical matching becomes difficult and defect-free large memories become difficult to manufacture
Solution Approach 1:
The patent combines two tunnel diodes into a single integrated structure where they share common diffusion regions and are formed simultaneously in the same semiconductor substrate. This merging approach ensures that both diodes experience identical manufacturing conditions, thereby achieving excellent electrical matching while maintaining high speed performance and compact size.
Solution Approach 2:
The patent creates local symmetry in the diode structure by using identical diffusion conditions, contact configurations, and geometric dimensions for both tunnel diodes within the memory cell. This local quality control ensures that electrical characteristics are matched precisely, resolving the manufacturing precision issue while preserving the high-speed benefits of tunnel diodes.
2Device complexity
If capacitive coupling to data lines is implemented, then memory structure is formed, but integration with high-frequency, high-density SRAM memory arrays is not efficient
Solution Approach 1:
The patent transitions from planar capacitor configurations to vertically stacked capacitor structures that extend in the third dimension. This dimensional change allows for higher capacitance values in a smaller footprint, enabling efficient integration with high-density SRAM arrays while maintaining the capacitive coupling functionality for data line interaction.
Solution Approach 2:
The patent nests the capacitor structure within the tunnel diode memory cell architecture, where the capacitor is integrated alongside the diodes in a compact three-dimensional arrangement. This nesting approach maximizes space utilization and achieves efficient integration with high-frequency, high-density memory arrays without compromising the capacitive coupling mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes manufacturing costs and variations, enabling the production of high-density, high-speed tunnel diode memory arrays with improved electrical matching and reduced defect rates, allowing for efficient data writing and reading with minimal external signals.
Implementation Method 1
coupled to a data line through a capacitor
Data Source
AI summary
A design of a non-transistor memory core with corresponding shift register control logic may be all comprised of tunnel diodes and capacitors, and a method for fabricating such memories and control logic may use a stencil and non-lithographic self-aligning semiconductor processing steps to minimize cost. Designs and fabrication processes for I/O pads connected to the memory core and control logic are also presented.