Tunnel Insulation Layer Silicon Interlayer for Low Erase Voltage

Solution Overview

Problem

Existing semiconductor devices face challenges in achieving reliable operational and mechanical stability in the tunnel insulation layer, particularly in reducing erase voltage while minimizing charge loss, due to the charge trap properties of nitride layers used in tunnel insulation layers.

Innovation Solution

A semiconductor device with a tunnel insulation layer comprising a first silicon oxide layer, a silicon layer, and a second silicon oxide layer, where the silicon layer has a thickness smaller than the oxide layers, is used to reduce valence band offset and charge trap properties, allowing for efficient erase operations with lower erase voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a nitride layer is used in the tunnel insulation layer, then charge trap properties are enhanced, but erase voltage increases and charge loss occurs

Engineering Contradiction:

Improveoperational stabilityVSAvoiderase voltage

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent removes the nitride layer from the tunnel insulation layer structure, extracting the harmful charge trap properties while maintaining the essential insulation function through oxide layers only. This eliminates the source of high erase voltage and charge loss while preserving operational stability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs a composite oxide-oxide structure (first oxide layer and second oxide layer) to replace the previous oxide-nitride-oxide composite structure. This new composite material approach achieves the desired insulation properties without introducing charge trap issues, thereby reducing erase voltage and preventing charge loss.

Inventive Principle:

Principle #40Composite materials

2Reliability

If a nitride layer is used in the tunnel insulation layer, then charge trap properties are enhanced, but charge loss increases

Engineering Contradiction:

Improveoperational stabilityVSAvoidcharge loss

Core Design Contradiction:

ReliabilityVSLoss of substance

Solution Approach 1:

The patent removes the nitride layer from the tunnel insulation layer structure, extracting the harmful charge trap properties while maintaining the essential insulation function through oxide layers only. This eliminates the source of high erase voltage and charge loss while preserving operational stability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs a composite oxide-oxide structure (first oxide layer and second oxide layer) to replace the previous oxide-nitride-oxide composite structure. This new composite material approach achieves the desired insulation properties without introducing charge trap issues, thereby reducing erase voltage and preventing charge loss.

Inventive Principle:

Principle #40Composite materials

3Use of energy by moving object

If the silicon layer thickness is increased, then valence band offset is reduced, but charge trap properties may increase

Engineering Contradiction:

Improveerase voltageVSAvoidcharge trap properties

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent precisely controls the thickness parameter of the silicon layer to be between 1 nm and 3 nm. This parameter optimization achieves sufficient valence band offset reduction for effective erase operations while maintaining thin enough dimensions to prevent excessive charge trapping, thus balancing both requirements.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent creates a localized thin silicon layer structure with specific thickness characteristics that differ from the surrounding oxide layers. This local structural optimization provides the necessary band offset properties in the critical region without introducing widespread charge trap issues throughout the entire tunnel insulation layer.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces erase voltage and minimizes charge loss, enhancing operational and mechanical reliability of semiconductor devices by using a silicon layer with low charge trap properties as an intermediate layer in the tunnel insulation layer.

Implementation Method 1

the silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer to reduce a valence band offset of a band-gap

Methodology Applied

Scientific EffectValence band offset reduction:

Implementation Method 2

the silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer to reduce a valence band offset of a band-gap and charge trap properties

Methodology Applied

Scientific EffectCharge trap property reduction:

Data Source

PatentUS9991281B2Semiconductor devices and methods of manufacturing the same

Publication Date: 2018.06.05 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.