Tunnel-Junction LED Stack for Lower Forward Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current light-emitting elements have high forward voltage, which is undesirable and needs to be reduced.
Innovation Solution
A light-emitting element with a semiconductor stack comprising nitride semiconductors, including a first and second light-emitting unit with specific n-type and p-type semiconductor layers, and a tunnel junction layer, where the n-type impurity concentration in the second stack part is higher than in the first stack part, reducing the depletion layer width and forward voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Force
If conventional n-side semiconductor layers with uniform or low n-type impurity concentration are used, then the depletion layer width is larger, but the forward voltage becomes higher
Solution Approach 1:
The n-side semiconductor layer is segmented into multiple stacked regions (first through fourth stack parts) with progressively increasing n-type impurity concentrations. This segmentation allows the depletion layer width to be controlled in a graded manner, reducing the forward voltage by creating more favorable carrier distribution while maintaining manufacturing precision through systematic concentration gradients.
Solution Approach 2:
The n-type impurity concentration parameter is systematically changed across different stack parts of the n-side semiconductor layer. By increasing the impurity concentration from the first to the fourth stack part, the electrical properties are optimized to reduce the depletion layer width and consequently lower the forward voltage, while maintaining control over the layer structure.
2Force
If the n-type impurity concentration is increased to reduce forward voltage, then the depletion layer width decreases, but the lattice mismatch and dislocation density may increase
Solution Approach 1:
Different regions (stack parts) of the n-side semiconductor layer are assigned different n-type impurity concentrations according to their specific functional requirements. The first stack part has lower concentration suitable for reducing dislocation density, while subsequent stack parts have progressively higher concentrations to reduce depletion layer width and forward voltage, optimizing both crystal quality and electrical performance locally.
Solution Approach 2:
The first stack part with lower n-type impurity concentration is formed first to establish a foundation with reduced dislocation density. Subsequent stack parts with higher impurity concentrations are then formed on top, building upon the improved crystal quality while achieving the desired electrical characteristics for forward voltage reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces the forward voltage while maintaining output, as demonstrated by a 0.13 V reduction in forward voltage compared to a comparative example, with similar output performance.
Implementation Method 1
a tunnel junction layer disposed between the first p-side semiconductor layer and the second n-side semiconductor layer
Implementation Method 2
first layers and second layers having a different lattice constant from that of the first layers are alternately stacked
Data Source
AI summary
A light-emitting element includes: a semiconductor stack including: a first light-emitting unit comprising nitride semiconductors including a first n-side semiconductor layer, a first p-side semiconductor layer, and a first active layer disposed between the first n-side semiconductor layer and the first p-side semiconductor layer, a second light-emitting unit comprising nitride semiconductors including a second n-side semiconductor layer, a second p-side semiconductor layer, and a second active layer disposed between the second n-side semiconductor layer and the second p-side semiconductor layer, and a tunnel junction layer disposed between the first p-side semiconductor layer and the second n-side semiconductor layer; an n-side electrode electrically connected to the first n-side semiconductor layer; and a p-side electrode electrically connected to the second p-side semiconductor layer.