Tunnel-Junction Layered Structure for Ohmic Contact on Ge

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Solution Overview

Problem

The fermi level pinning effect in n-type Ge substrates makes it challenging to form ohmic contacts, leading to increased resistance and losses in devices fabricated using III-V semiconductor materials, limiting the use of such substrates for growing III-V semiconductor layers.

Innovation Solution

A layered structure with a p-type semiconductor substrate and a tunnel junction layer, such as a n-on-p tunnel junction, is introduced to enable charge carriers to tunnel across the barrier, facilitating ohmic contacting and reducing resistance and losses, while maintaining low strain properties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If n-type Ge substrates are used to grow III-V semiconductor layers, then the substrate can be doped to act as a low-resistance material, but the fermi level pinning effect prevents ohmic contacts from being easily formed, leading to increased resistance and losses

Engineering Contradiction:
Improvedevice performanceVSAvoidcontact fabrication
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

An n-type tunnel junction layer is introduced as an intermediary between the p-type substrate and the n-type semiconductor layers. This tunnel junction layer enables charge carrier tunneling across the p-n interface, effectively mediating the electrical connection and allowing ohmic contacting to be achieved without the fermi level pinning problem that would otherwise prevent it.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If a p-type substrate is used to avoid fermi level pinning, then ohmic contacts can be formed, but a p-on-n junction structure is required which may introduce additional complexity

Engineering Contradiction:
Improvecontact fabricationVSAvoidjunction structure
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The n-type tunnel junction layer serves as a mediator that enables the p-type substrate to function effectively with n-type device structures. By facilitating charge carrier tunneling, it allows the substrate to be contacted ohmically while maintaining compatibility with the n-type semiconductor layers, thus resolving the complexity issue.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stability of the object's composition

If III-V semiconductor materials are grown on group IV semiconductor substrates, then desirable low strain properties can be achieved, but the fermi level pinning effect in n-type Ge substrates limits their use

Engineering Contradiction:
Improvestrain propertiesVSAvoiddevice performance
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The substrate doping type is changed from n-type to p-type to eliminate the fermi level pinning effect. This parameter change allows III-V semiconductor materials to be grown on group IV substrates like Ge while achieving both desirable low strain properties and reliable device performance through ohmic contacting.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The tunnel junction layer allows for low-resistance and low-loss devices by enabling charge carrier tunneling across the barrier, reducing processing steps, and allowing for the use of p-type Ge substrates with low strain properties, thereby improving device performance.

Implementation Method 1

a tunnel junction layer between the substrate and the plurality of semiconductor layers... enables charge carriers to tunnel across the barrier

Methodology Applied
Scientific EffectCharge carrier tunneling: Josephson Effect

Data Source

PatentEP4322347A1Layered structure
Publication Date: 2024.02.14 IQE
  • EP4322347A1 patent drawingFigure 1
  • EP4322347A1 patent drawingFigure 2
  • EP4322347A1 patent drawingFigure 3

AI summary

The present disclosure relates to a layered structure (200, 300) comprising: a substrate (110) comprising a p-type semiconductor material; a plurality of semiconductor layers (120), on the substrate (110), comprising at least one p-on-n junction; and a tunnel junction layer (130) between the substrate (110) and the plurality of semiconductor layers.