Tunnel polarization junction III-N transistors
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Solution Overview
Problem
Current techniques fail to produce high-performance p-channel III-N transistors, particularly gallium nitride (GaN) transistors, due to challenges in achieving high p-doping in source and drain materials, leading to poor contact resistance and integration issues with n-channel transistors, which is critical for power management and radio frequency integrated circuits.
Innovation Solution
The development of tunnel polarization junction III-N transistors with crystalline III-N material layers having inverted crystal orientations, creating a high-density 2D hole gas or electron gas at the interfaces, which improves the p-channel transistor performance by enhancing the polarization properties and allowing for better integration with n-channel transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional p-doping techniques are used in III-N source and drain materials, then fabrication process remains simple, but contact resistance is poor and transistor performance is limited
Solution Approach 1:
The patent changes the doping parameter from conventional p-type doping to n-type doping in the source and drain regions, achieving dopant concentrations up to 5×10^19/cm³. This parameter change transforms the contact properties and enables low contact resistance without requiring new fabrication techniques, as n-type doping is well-established in III-N technology.
Solution Approach 2:
The patent converts the limitation of maximum achievable p-doping concentration into a benefit by using n-type doping instead. The previously problematic low p-doping levels (5×10^17/cm³) are transformed into an advantage by employing n-type dopants at high concentrations, which provide superior electrical contact properties and enable high-performance p-channel transistors.
2Reliability
If high p-doping is achieved in III-N source and drain materials, then contact resistance improves, but fabrication complexity increases
Solution Approach 1:
The patent employs n-type doping with concentrations up to 5×10^19/cm³ in source and drain regions, achieving excellent contact properties. This approach avoids the fabrication complexity associated with achieving high p-doping levels, as n-type doping is a成熟 process in III-N technology that can be implemented using standard diffusion or ion implantation techniques.
3Adaptability or versatility
If p-channel III-N transistors are fabricated with conventional methods, then integration with n-channel transistors is attempted, but integration problems persist
Solution Approach 1:
The patent applies different doping types to different regions: n-type doping in source and drain regions for both p-channel and n-channel transistors, and appropriate channel doping for each transistor type. This local quality approach enables compatible fabrication processes and reliable integration, as the same n-type source/drain formation technique can be used for both transistor types while maintaining their distinct electrical characteristics.
4Length of moving object
If GaN transistors are scaled to smaller dimensions, then operating voltage capability is maintained, but hole mobility limitations become more critical
Solution Approach 1:
The patent employs high concentration n-type doping (up to 5×10^19/cm³) in source and drain regions, which creates strong electric fields that enhance hole injection efficiency into the channel. This parameter change in doping concentration compensates for the inherent low hole mobility in GaN, enabling scaled devices to maintain performance by improving carrier injection rather than relying on bulk hole mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-performance p-channel III-N transistors with improved mobility and efficiency, facilitating all-III-N CMOS implementations that span low to high voltage applications, enhancing power management and radio frequency performance.
Implementation Method 1
tunnel polarization junction III-N transistors with inverted crystal orientations, creating a high-density 2D hole gas or electron gas at the interfaces, which improves the p-channel transistor performance by enhancing the polarization properties
Data Source
AI summary
Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.