Tunnel Nanosheet TFET Structure for Higher Tunneling Current
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Solution Overview
Problem
Conventional FET technologies face challenges with increasing power consumption and limited performance improvements due to leakage currents and material limitations, necessitating the development of alternative transistor designs like TFETs that leverage quantum mechanical tunneling.
Innovation Solution
A Tunnel Field-Effect Transistor (TFET) design incorporating a gate stack, channel region, and protruding nanosheets with a narrow bandgap material, where tunneling occurs through multiple surfaces, enhancing tunneling current and reducing power consumption by increasing the tunneling area and improving charge carrier transport.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional FET structures are used, then manufacturing is simpler, but power consumption increases and performance is limited due to leakage currents
Solution Approach 1:
The channel is segmented into multiple nanosheet structures (e.g., three nanosheets per device) stacked vertically, with each nanosheet providing a separate conduction path. This segmentation increases the effective channel area and reduces leakage current by distributing the current flow across multiple isolated pathways, directly addressing the power consumption issue while maintaining manageable complexity through modular fabrication
Solution Approach 2:
The invention transitions from a planar 2D channel structure to a 3D vertical nanosheet architecture. The nanosheets extend vertically from the substrate, creating a three-dimensional conduction path that increases the effective channel area without increasing the lateral footprint. This dimensional change enables reduced leakage and improved performance while the vertical stacking maintains manufacturing feasibility through established epitaxial growth techniques
2Productivity
If planar transistor architecture is used, then device density is lower, but manufacturing and control are simpler
Solution Approach 1:
The planar 2D channel is replaced with vertical 3D nanosheet structures that extend upward from the substrate. Multiple nanosheets are stacked vertically within the same lateral footprint, effectively multiplying the channel area by the number of nanosheets. This dimensional transition achieves high device density without requiring larger chip areas, while the regular stacked geometry maintains compatibility with standard fabrication processes
Solution Approach 2:
Multiple nanosheet channels are nested vertically within a single device footprint, with each nanosheet containing a gate stack wrapped around it. The nanosheets are positioned one above another in a nested arrangement, maximizing the use of vertical space to increase device density. This nesting approach allows multiple functional channels to occupy the same lateral area while maintaining independent control through individual gate stacks
3Reliability
If narrow bandgap material is used in nanosheets, then tunneling current increases, but material selection and fabrication become more difficult
Solution Approach 1:
The narrow bandgap material (such as Ge or SiGe) is applied locally only to the nanosheet channel regions where tunneling is required, rather than throughout the entire device. The first layer in each nanosheet contains the narrow bandgap material with controlled thickness and composition, while other regions use conventional materials. This localized application achieves the desired tunneling current enhancement while simplifying fabrication by limiting complex material processing to specific areas
Solution Approach 2:
The nanosheet structure employs composite material layers, with a first layer containing narrow bandgap material (Ge, SiGe, GaAs, InAs, or InGaAs) encapsulated by or combined with other semiconductor materials. This composite approach allows optimization of tunneling properties in the narrow bandgap region while using conventional materials for other functions, balancing performance requirements with manufacturing feasibility through material composition gradients and heterostructure design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The TFET achieves low off-current and high on-current, reduced power consumption, and improved energy efficiency with enhanced on/off current ratio and subthreshold swing, making it suitable for low-power logic circuits and RF devices.
Implementation Method 1
Tunnel Field-Effect Transistor (TFET) design incorporating a gate stack, channel region, and protruding nanosheets with a narrow bandgap material, where tunneling occurs through multiple surfaces
Data Source
AI summary
A Tunnel Field-Effect Transistor (TFET) device, an isolating layer over a substrate layer, a gate stack above the isolating layer, a source and a drain region over the isolating layer, a channel region underneath the gate stack, and a plurality of nanosheets in the channel region protruding from the source region. Each nanosheet of the plurality of nanosheets includes source region material encapsulated by a narrow band gap material.