Tunnel Structure for Nonvolatile Memory Erase Disturb
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Solution Overview
Problem
Conventional nonvolatile memory arrays face issues with erase disturb and reliability due to the use of additional layers and the need for separate charge storage and control gate layers, which increase costs and reduce yield.
Innovation Solution
A novel memory architecture with a tunnel structure that allows charge carriers to tunnel through different dielectric layers within a memory cell, improving reliability by reducing dielectric failure and preventing data disturbance in unselected memory cells during erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional layers and separate charge storage and control gate layers are used in conventional nonvolatile memory, then charge storage capability is improved, but manufacturing cost increases and production yield decreases
Solution Approach 1:
The patent combines the charge storage layer and control gate layer into a single integrated structure where the polysilicon layer serves dual functions. The same polysilicon layer that forms the control gate for transistors also serves as the charge storage layer for nonvolatile memory cells, eliminating the need for separate layers and reducing manufacturing complexity while maintaining charge storage capability
Solution Approach 2:
The polysilicon layer is designed to perform multiple functions simultaneously: it acts as the control gate electrode for transistor operation and as the charge storage layer for nonvolatile memory functionality. This multi-functional design reduces the number of additional layers needed and simplifies the manufacturing process
2Reliability
If additional layers and separate charge storage and control gate layers are used in conventional nonvolatile memory, then charge storage capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the charge storage layer and control gate layer into a single polysilicon layer, eliminating the need for additional deposition and processing steps that would increase manufacturing cost. The integrated structure uses the same material and processing for both functions
Solution Approach 2:
The polysilicon layer is designed to serve dual purposes as both control gate and charge storage layer, making the manufacturing process more efficient and cost-effective by eliminating redundant layers and processing steps
3Ease of operation
If conventional nonvolatile memory architecture is used, then memory functionality is achieved, but erase disturb issues occur in unselected memory cells
Solution Approach 1:
The patent segments the dielectric structure into multiple distinct layers: a first dielectric layer adjacent to the polysilicon layer and a second dielectric layer adjacent to the substrate. This segmentation allows different dielectric materials to be used in different regions, optimizing each layer's properties for its specific function and reducing erase disturb effects
Solution Approach 2:
The patent applies different dielectric materials with different properties in different locations: the first dielectric layer uses a material optimized for charge storage and tunneling, while the second dielectric layer uses a material optimized for electrical isolation and reducing disturb effects. Each location has dielectric properties tailored to its specific functional requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances the reliability and reduces erase disturb issues by allowing charge carriers to tunnel through different dielectric layers, thereby extending the lifespan of the memory array and maintaining data integrity.
Implementation Method 1
a tunnel structure that allows charge carriers to tunnel through different dielectric layers within a memory cell
Data Source
AI summary
An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.