Tunnel Transistor Pass Gate for SRAM Power Reduction
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Solution Overview
Problem
Miniaturization of LSIs using MISFETs makes it difficult to reduce power supply voltage and leakage current, hindering the realization of low-power consumption LSIs, as tunnel transistors with different conductivity type source and drain regions struggle to effectively cut off bidirectional current.
Innovation Solution
The implementation of a pass gate using two tunnel transistors with conductivity type diffusion regions and a shared gate electrode, where the source and drain regions of each transistor are electrically connected, allowing for bidirectional current cutoff and flow control through voltage manipulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a single tunnel transistor is used in a pass gate to replace MISFET, then power consumption can be reduced and power supply voltage can be lowered, but bidirectional current cannot be cut off effectively
Solution Approach 1:
The pass gate is divided into two separate tunnel transistors (first and second tunnel transistors) instead of using a single tunnel transistor. Each transistor handles one direction of current flow, with their source/drain regions electrically connected. This segmentation allows independent control of bidirectional current, enabling effective cutoff in both directions while maintaining the low power consumption benefits of tunnel transistors.
2Length of moving object
If miniaturization is progressed in MISFET-based LSI, then element size is reduced, but power supply voltage reduction and leakage current suppression become difficult
Solution Approach 1:
The invention changes the fundamental operating parameters of the transistor by using tunnel transistors instead of MISFETs. Tunnel transistors operate based on quantum tunneling effects rather than conventional field effect, enabling steep Id-Vg characteristics that allow for lower power supply voltages. This parameter change in the transistor mechanism enables continued power reduction even as element size is miniaturized.
3Speed
If tunnel transistors with different conductivity type source and drain regions are used, then steep Id-Vg characteristics are achieved, but bidirectional current control is compromised
Solution Approach 1:
Each tunnel transistor maintains its asymmetric structure with different conductivity type source and drain regions, which provides steep Id-Vg characteristics for fast switching. The overall pass gate achieves bidirectional control through the symmetric arrangement of two such asymmetric transistors, with their source/drain regions electrically connected to handle opposite current directions. This combines asymmetry at the device level with symmetry at the circuit level.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the cutoff characteristics of the pass gate, reducing power consumption and production costs by utilizing tunnel transistors as all transistors in semiconductor storage devices, while preventing erroneous writes in SRAM cells.
Implementation Method 1
a three-terminal tunnel transistor controls a tunnel current of a p-n junction made between a drain and a source by a gate voltage
Data Source
AI summary
According to an embodiment, a semiconductor storage device includes an SRAM cell. The SRAM cell includes first and second transfer gates each comprising a pass gate. The pass gate includes first and second tunnel transistors. The first tunnel transistor includes a first conductivity type first diffusion region as a source or drain region, a second conductivity type second diffusion region as a drain or source region, and a gate electrode supplied with a control voltage. The second tunnel transistor includes a first conductivity type first diffusion region as a source or drain region, a second conductivity type second diffusion region as a drain or source region electrically connected to the second diffusion region of the first tunnel transistor, and a gate electrode electrically connected to the gate electrode of the first tunnel transistor.